Andreas G. Veneris Home Page Coauthor index pubzone.org

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c64Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Bao Le, Dipanjan Sengupta, Andreas G. Veneris: Reviving erroneous stability-based clock-gating using partial Max-SAT. ASP-DAC 2013: 717-722
2012
j20Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm: Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 271-284 (2012)
j19Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici: Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. IEEE Trans. VLSI Syst. 20(6): 1118-1131 (2012)
c63Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita: Automated data analysis techniques for a modern silicon debug environment. ASP-DAC 2012: 298-303
c62Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita: On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC 2012: 695-700
c61Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Brian Keng, Andreas G. Veneris: Path directed abstraction and refinement in SAT-based design debugging. DAC 2012: 947-954
c60Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Zissis Poulos, Yu-Shen Yang, Jason Anderson, Andreas G. Veneris, Bao Le: Leveraging reconfigurability to raise productivity in FPGA functional debug. DATE 2012: 292-295
c59Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris: Non-solution implications using reverse domination in a modern SAT-based debugging environment. DATE 2012: 629-634
c58Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Brian Keng, Andreas G. Veneris: Automated debugging of missing input constraints in a formal verification environment. FMCAD 2012: 101-105
c57Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, André Ivanov: Lazy suspect-set computation: fault diagnosis for deep electrical bugs. ACM Great Lakes Symposium on VLSI 2012: 189-194
2011
j18Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton: Automating Logic Transformations With Approximate SPFDs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(5): 651-664 (2011)
j17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Elham Safi, Andreas Moshovos, Andreas G. Veneris: Two-Stage, Pipelined Register Renaming. IEEE Trans. VLSI Syst. 19(10): 1926-1931 (2011)
c56Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Brian Keng, Sean Safarpour: From RTL to silicon: The case for automated debug. ASP-DAC 2011: 306-310
c55Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Brian Keng, Andreas G. Veneris: Managing complexity in design debugging with sequential abstraction and refinement. ASP-DAC 2011: 479-484
c54Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Brian Keng, Sean Safarpour, Andreas G. Veneris: Automated debugging of SystemVerilog assertions. DATE 2011: 323-328
c53Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Resve A. Saleh: Sequence pair based voltage island floorplanning. IGCC 2011: 1-6
c52Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour: Debugging with dominance: On-the-fly RTL debug solution implications. ICCAD 2011: 587-594
2010
j16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Hratch Mangassarian, Andreas G. Veneris, Marco Benedetti: Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test. IEEE Trans. Computers 59(7): 981-994 (2010)
j15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Brian Keng, Sean Safarpour, Andreas G. Veneris: Bounded Model Debugging. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1790-1803 (2010)
j14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yibin Chen, Sean Safarpour, João Marques-Silva, Andreas G. Veneris: Automated Design Debugging With Maximum Satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1804-1817 (2010)
j13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Elham Safi, Andreas Moshovos, Andreas G. Veneris: On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. IEEE Trans. VLSI Syst. 18(3): 365-377 (2010)
c51Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Andreas G. Veneris, Farid N. Najm: Managing verification error traces with bounded model debugging. ASP-DAC 2010: 601-606
c50Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus: Leveraging dominators for preprocessing QBF. DATE 2010: 1695-1700
c49Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour: Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED 2010: 675-682
c48Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Brian Keng, Andreas G. Veneris, Sean Safarpour: An Automated Framework for Correction and Debug of PSL Assertions. MTV 2010: 9-12
2009
j12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Andreas G. Veneris: Automated Design Debugging With Abstraction and Refinement. IEEE Trans. on CAD of Integrated Circuits and Systems 28(10): 1597-1608 (2009)
c47Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Sean Safarpour: The day Sherlock Holmes decided to do EDA. DAC 2009: 631-634
c46Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris: Automated data analysis solutions to silicon debug. DATE 2009: 982-987
c45Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith: Sequential logic rectifications with approximate SPFDs. DATE 2009: 1698-1703
c44Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Brian Keng, Andreas G. Veneris: Scaling VLSI design debugging with interpolation. FMCAD 2009: 144-151
c43Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yibin Chen, Sean Safarpour, Andreas G. Veneris, João P. Marques Silva: Spatial and temporal design debug using partial MaxSAT. ACM Great Lakes Symposium on VLSI 2009: 345-350
c42Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Andreas G. Veneris: Automated debugging with high level abstraction and refinement. HLDVT 2009: 26-31
c41Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Elham Safi, Andreas Moshovos, Andreas G. Veneris: A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. ICSAMOS 2009: 41-48
2008
j11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: Improved SAT-based Reachability Analysis with Observability Don't Cares. JSAT 5(1-4): 1-25 (2008)
j10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Elham Safi, Andreas Moshovos, Andreas G. Veneris: L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture. IEEE Trans. VLSI Syst. 16(6): 628-638 (2008)
c40Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Brian Keng, Hratch Mangassarian, Andreas G. Veneris: A succinct memory model for automated design debugging. ICCAD 2008: 137-142
c39Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris: On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. IOLTS 2008: 123-128
c38Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Elham Safi, Andreas Moshovos, Andreas G. Veneris: A physical level study and optimization of CAM-based checkpointed register alias table. ISLPED 2008: 233-236
2007
c37Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton: Automating Logic Rectification by Approximate SPFDs. ASP-DAC 2007: 402-407
c36Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian: Trace Compaction using SAT-based Reachability Analysis. ASP-DAC 2007: 932-937
c35Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Andreas G. Veneris: Abstraction and refinement techniques in automated design debugging. DATE 2007: 1182-1187
c34Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir: Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE 2007: 1538-1543
c33Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah: Improved Design Debugging Using Maximum Satisfiability. FMCAD 2007: 13-19
c32Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith: A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. ICCAD 2007: 240-245
c31Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni: On the latency, energy and area of checkpointed, superscalar register alias tables. ISLPED 2007: 379-382
2006
j9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman: Extraction error modeling and automated model debugging in high-performance custom designs. IEEE Trans. VLSI Syst. 14(7): 763-776 (2006)
c30Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan: Efficient SAT-based Boolean matching for FPGA technology mapping. DAC 2006: 466-471
c29Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: On the relation between simulation-based and SAT-based diagnosis. DATE 2006: 1139-1144
c28Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: Integrating observability don't cares in all-solution SAT solvers. ISCAS 2006
c27Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Elham Safi, Andreas Moshovos, Andreas G. Veneris: L-CBF: a low-power, fast counting bloom filter architecture. ISLPED 2006: 250-255
c26Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris: Seamless Integration of SER in Rewiring-Based Design Space Exploration. ITC 2006: 1-9
c25Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Andreas G. Veneris: Abstraction and Refinement Techniques in Automated Design Debugging. MTV 2006: 88-93
c24Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Yiorgos Makris: Session Abstract. VTS 2006: 290-291
2005
j8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Jiang Brandon Liu: Incremental Design Debugging in a Logic Synthesis Environment. J. Electronic Testing 21(5): 485-494 (2005)
j7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi: Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. J. Electronic Testing 21(5): 495-502 (2005)
j6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Jiang Brandon Liu, Andreas G. Veneris: Incremental fault diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 240-251 (2005)
j5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Alexander Smith, Andreas G. Veneris, Moayad Fahim Ali, Anastasios Viglas: Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1606-1621 (2005)
c23Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman: Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. DATE 2005: 996-1001
c22Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour: Diagnosing multiple transition faults in the absence of timing information. ACM Great Lakes Symposium on VLSI 2005: 193-196
c21Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler: Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI 2005: 264-269
c20no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-verification debugging of hierarchical designs. ICCAD 2005: 871-876
c19Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47
2004
j4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris: Logic Rewiring for Delay and Power Minimization. J. Inf. Sci. Eng. 20(6): 1231-1238 (2004)
c18Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Alexander Smith, Andreas G. Veneris, Anastasios Viglas: Design diagnosis using Boolean satisfiability. ASP-DAC 2004: 218-223
c17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee: Managing Don't Cares in Boolean Satisfiability. DATE 2004: 260-265
c16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir: Debugging sequential circuits using Boolean satisfiability. ICCAD 2004: 204-209
c15no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri: Fault equivalence and diagnostic test generation using ATPG. ISCAS (5) 2004: 221-224
c14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith: Debugging Sequential Circuits Using Boolean Satisfiability. MTV 2004: 44-49
2003
c13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Alexander Smith, Magdy S. Abadir: Logic verification based on diagnosis techniques. ASP-DAC 2003: 93-98
c12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris: Extraction Error Diagnosis and Correction in High-Performance Designs. ITC 2003: 423-430
c11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris: Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. MTV 2003: 54-59
c10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris: Fault Diagnosis and Logic Debugging Using Boolean Satisfiability. MTV 2003: 60-
2002
j3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Magdy S. Abadir: Design rewiring using ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1469-1479 (2002)
c9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir: Incremental Diagnosis and Correction of Multiple Faults and Errors. DATE 2002: 716-721
c8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Mandana Amiri, Andreas G. Veneris, Ivor Ting: Design rewiring for power minimization [logic design]. ISCAS (4) 2002: 305-308
c7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri: Design Rewiring Using ATPG. ITC 2002: 223-232
c6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Jiang Brandon Liu, Andreas G. Veneris, Hiroshi Takahashi: Incremental Diagnosis of Multiple Open-Interconnects. ITC 2002: 1085-1092
2001
c5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Magdy S. Abadir, Ivor Ting: Design rewiring based on diagnosis techniques. ASP-DAC 2001: 479-484
1999
j2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Ibrahim N. Hajj: Design error diagnosis and correction via test vector simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1803-1816 (1999)
c4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Ibrahim N. Hajj: Correcting multiple design errors in digital VLSI circuits. ISCAS (1) 1999: 31-34
c3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs: Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. VTS 1999: 58-63
1997
c2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Andreas G. Veneris, Ibrahim N. Hajj: A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. Great Lakes Symposium on VLSI 1997: 45-50
1995
j1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Lefteris M. Kirousis, Andreas G. Veneris: Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations. Acta Inf. 32(2): 155-170 (1995)
1993
c1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Lefteris M. Kirousis, Andreas G. Veneris: Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations. WDAG 1993: 54-68

Coauthor Index

1Magdy S. Abadir
[c34] [j7] [c22] [c20] [c19] [c16] [c15] [c14] [c13] [j3] [c9] [c7] [c5]
2Patrick Akl
[c31]
3Moayad Fahim Ali
[j5] [c20] [c19] [c16] [c14]
4Sobeeh Almukhaizim
[c39] [c26]
5Mandana Amiri
[c15] [c9] [c8] [c7]
6Jason Anderson
[c60]
7Angela Arapoyanni (Aggeliki Arapoyanni)
[c31]
8Fahiem Bacchus
[c50]
9Gregg Baeckler
[c30]
10Marco Benedetti
[j16] [c32]
11Robert K. Brayton
[j18] [c45] [c37]
12Robert Chang
[j7] [c15]
13Yibin Chen
[j14] [c43]
14Rolf Drechsler
[j11] [c29] [c28] [c21] [c20] [c19] [c17] [c16] [c14]
15Görschwin Fey
[c29] [c21]
16W. Kent Fuchs
[c3]
17Masahiro Fujita
[c63] [c62]
18Alexandra Goultiaeva
[c50]
19Ibrahim N. Hajj
[j2] [c4] [c3] [c2]
20Alan J. Hu
[c57]
21André Ivanov
[c57] [c53]
22Brian Keng
[c61] [c59] [c58] [c56] [c55] [c54] [j15] [c49] [c48] [c44] [c40]
23Lefteris M. Kirousis
[j1] [c1]
24Bao Le
[c64] [c60] [c59] [c50]
25Joanne Lee
[c17]
26Mark H. Liffiton
[c33]
27Jiang Brandon Liu
[j8] [j6] [c22] [c12] [c11] [c9] [c6]
28Yiorgos Makris
[c39] [c26] [c24]
29Hratch Mangassarian
[j20] [c62] [c59] [c52] [j16] [c50] [c40] [c36] [c34] [c33] [c32]
30Joao Marques-Silva (João P. Marques Silva, João Marques-Silva)
[j14] [c43]
31Andreas Moshovos
[j17] [j13] [c41] [j10] [c38] [c31] [c27]
32Farid N. Najm
[j20] [c51] [c34]
33Nicola Nicolici
[j19] [c63] [c49] [c46]
34Flavio M. de Paula
[c57]
35Zissis Poulos
[c60]
36Sean Safarpour
[c56] [c54] [c52] [j15] [j14] [c51] [c49] [c48] [j12] [c47] [c43] [c42] [j11] [c36] [c35] [c34] [c33] [c32] [c30] [c29] [c28] [c25] [c22] [c21] [c20] [c19] [c17] [c16] [c14]
37Elham Safi
[j17] [j13] [c41] [j10] [c38] [c31] [c27]
38Karem A. Sakallah
[c33]
39Resve A. Saleh (Resve Saleh, Res Saleh)
[c53]
40Freescale Semiconductor
[c14]
41Dipanjan Sengupta
[c64] [c57] [c53]
42Sep Seyedi
[j7]
43Subarna Sinha
[j18] [c45]
44Subarnarekha Sinha
[c37]
45Alexander Smith
[j5] [c18] [c16] [c14] [c13]
46Duncan Exon Smith
[c52] [c45] [c32]
47Hiroshi Takahashi
[c6]
48Paul J. Thadikaran
[j9] [c23] [c12] [c11]
49Ivor Ting
[c8] [c5]
50Srikanth Venkataraman
[j9] [c23] [c3]
51Anastasios Viglas
[j5] [c18]
52Steven J. E. Wilton
[c53]
53Shigeru Yamashita
[c62]
54Yu-Shen Yang
[j19] [c63] [c60] [j18] [c49] [c46] [c45] [c39] [c37] [j9] [c26] [c23] [c12] [c11]
55Hiroaki Yoshida
[c62]
56Richard Yuan
[c30]
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