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Nagarajan Venkateswaran
2010 – today
- 2012
[c9]Nagarajan Venkateswaran, Rajagopal Hariharan, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Vigneshwaran Sankaran, Bharanidharan Vasudevan, Ravindhiran Mukundrajan, Nachiappan Chidambaram Nachiappan, Aswin Sridharan, Karthikeyan P. Saravanan, Vignesh Adhinarayanan, Vignesh Veppur Sankaranarayanan: SCOC IP Cores for Custom Built Supercomputing Nodes. ISVLSI 2012: 255-260- [c8]Nagarajan Venkateswaran, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Rajagopal Hariharan, Bharanidharan Vasudevan, Nachiappan Chidambaram Nachiappan, Karthikeyan P. Saravanan, Aswin Sridharan, Vigneshwaran Sankaran, Vignesh Adhinarayanan, V. S. Vignesh, Ravindhiran Mukundrajan: Compilation Accelerator on Silicon. ISVLSI 2012: 267-272
- 2010
- [c7]Nagarajan Venkateswaran, Karthikeyan P. Saravanan, Nachiappan Chidambaram Nachiappan, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundrajan: Custom Built Heterogeneous Multi-core Architectures (CUBEMACH): Breaking the conventions. IPDPS Workshops 2010: 1-15
2000 – 2009
- 2009
- [j4]Nagarajan Venkateswaran, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundrajan, T. P. Ramnath Sai Sagar, Madhavan Manivannan, Sriram Murali, Vinoth Krishnan Elangovan: Towards modeling and integrated design automation of supercomputing clusters (MIDAS). Computer Science - R&D 24(1-2): 1-10 (2009)
- [c6]Nagarajan Venkateswaran, Ravindhiran Mukundrajan, Mrigank Sharma, Badrinarayanan Ravi: A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient. ISVLSI 2009: 49-54
- 2008
- [c5]Nagarajan Venkateswaran, Karthik Chandrasekar, Shrikanth Ganapathy: Design for Testability of Functional Cores in High Performance Node Architectures. DELTA 2008: 302-307
- [c4]Nagarajan Venkateswaran, Vinoth Krishnan Elangovan, Karthik Ganesan, T. R. S. Sagar, S. Aananthakrishanan, S. Ramalingam, Shyamsundar Gopalakrishnan, Madhavan Manivannan, Deepak Srinivasan, Viswanath Krishnamurthy, Karthik Chandrasekar, Viswanath Venkatesan, Balaji Subramaniam, V. Sangkar, Aravind Vasudevan, Shrikanth Ganapathy, Sriram Murali, M. Thyagarajan: On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system. IPDPS 2008: 1-8
- 2007
- [j3]Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Karthik Chandrasekar, Prem Kumar Ramesh, Viswanath Venkatesan, Arvindakshan Babu, Sudharshan: Future generation supercomputers I: a paradigm for node architecture. SIGARCH Computer Architecture News 35(5): 49-60 (2007)
- [j2]Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Arvind M, Prem Kumar Ramesh, Karthik Ganesan, Viswanath Krishnamurthy, Sivaramakrishnan: Future generation supercomputers II: a paradigm for cluster architecture. SIGARCH Computer Architecture News 35(5): 61-70 (2007)
- [c3]Nagarajan Venkateswaran, Arjun Kumeresh, Harish Chandran: DNA Based Evolutionary Approach for Microprocessor Design Automation. ICANNGA (1) 2007: 11-22
- 2006
- [c2]Arrvindh Shriraman, Nagarajan Venkateswaran, Niranjan Soundararajan: PASCOM: Power Model for Supercomputers. ARCS 2006: 326-340
- 2005
- [c1]Nagarajan Venkateswaran, Arrvindh Shriraman, Niranjan Soundararajan: Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance. IPDPS 2005
- 2004
- [j1]Nagarajan Venkateswaran, Aditya Krishnan, S. Niranjan Kumar, Arrvindh Shriraman, Srinivas Sridharan: Memory in processor: a novel design paradigm for supercomputing architectures. SIGARCH Computer Architecture News 32(3): 19-26 (2004)
Coauthor Index
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last updated on 2012-12-02 21:53 CET by the dblp team