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Julian Viejo
2010 – today
- 2012
[j6]Julian Viejo, Jose Ignacio Villar, J. Juan, Alejandro Millán, Enrique Ostúa, J. Quiros: Long-term on-chip verification of systems with logical events scattered in time. Microprocessors and Microsystems - Embedded Hardware Design 36(5): 402-408 (2012)- [c7]Jorge Juan, Julian Viejo, Manuel J. Bellido: Network Time Synchronization: A Full Hardware Approach. PATMOS 2012: 225-234
- 2011
- [j5]David Guerrero, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo: Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electronics 7(3): 444-452 (2011)
- [j4]Julian Viejo, Jorge Juan, Manuel Jesús Bellido Díaz, Alejandro Millán, Paulino Ruiz-de-Clavijo: Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation. IEEE T. Instrumentation and Measurement 60(12): 3961-3963 (2011)
- 2010
- [j3]Alejandro Millán, Manuel J. Bellido, Jorge Juan, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo: Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. J. Low Power Electronics 6(1): 93-102 (2010)
- [c6]Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Manuel Jesús Bellido Díaz, Enrique Ostúa: Design and implementation of a suitable core for on-chip long-term verification. SIES 2010: 234-237
2000 – 2009
- 2008
- [c5]Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo: Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS 2008: 389-398
- 2007
- [j2]David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo: Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electronics 3(1): 70-77 (2007)
- [c4]David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo: Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS 2007: 404-412
- [c3]Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa, A. Munoz: Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES 2007: 337-340
- 2006
- [j1]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero, Enrique Ostúa, Julian Viejo: Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electronics 2(1): 87-94 (2006)
- 2005
- [c2]Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo: Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS 2005: 337-347
- [c1]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo: Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS 2005: 425-435
Coauthor Index
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last updated on 2013-02-02 19:51 CET by the dblp team