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Heinrich Theodor Vierhaus
2010 – today
- 2013
[c58]Roberto Urban, Mario Schölzel, Heinrich Theodor Vierhaus: Ein konfigurierbarer Zwischencodesimulator zum compilerzentrierten Mikroprozessorentwurf. MBMV 2013: 13-24- [c57]Sebastian Müller, Mario Schölzel, Heinrich Theodor Vierhaus: Towards a Graceful Degradable Multicore-System by Hierarchical Handling of Hard Errors. PDP 2013: 302-309
- 2012
- [c56]Sebastian Müller, Mario Schölzel, Heinrich Theodor Vierhaus: Hierarchical Self-repair in Heterogeneous Multi-core Systems by Means of a Software-based Reconfiguration. ARCS Workshops 2012: 251-262
- [c55]Tobias Koal, Markus Ulbricht, Heinrich Theodor Vierhaus: Combining on-line fault detection and logic self repair. DDECS 2012: 288-293
- [c54]Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus: An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores. DDECS 2012: 312-317
- [c53]Markus Ulbricht, Heinrich Theodor Vierhaus, Tobias Koal: Activity Migration in M-of-N-Systems by Means of Load-Balancing. DSD 2012: 258-263
- [c52]Christian Gleichner, Heinrich Theodor Vierhaus, Piet Engelke: Scan Based Tests via Standard Interfaces. DSD 2012: 844-851
- [e3]Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin (Eds.): IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012. IEEE 2012, ISBN 978-1-4673-1187-8
- 2011
- [c51]Markus Ulbricht, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus: A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors. DDECS 2011: 143-146
- [c50]Tobias Koal, Heinrich Theodor Vierhaus: Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair. DDECS 2011: 219-224
- [c49]Tobias Koal, Daniel Scheit, Mario Schölzel, Heinrich Theodor Vierhaus: On the Feasibility of Built-In Self Repair for Logic Circuits. DFT 2011: 316-324
- [e2]Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus (Eds.): 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011. IEEE 2011, ISBN 978-1-4244-9755-3
- 2010
- [c48]Tobias Koal, Heinrich Theodor Vierhaus: A software-based self-test and hardware reconfiguration solution for VLIW processors. DDECS 2010: 40-43
- [c47]Tobias Koal, Heinrich Theodor Vierhaus: Combining de-stressing and self repair for long-term dependable systems. DDECS 2010: 99-104
- [c46]René Kothe, Heinrich Theodor Vierhaus: Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures. DSD 2010: 283-290
- [e1]Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann (Eds.): 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010. IEEE 2010, ISBN 978-1-4244-6612-2
2000 – 2009
- 2009
- [c45]Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus: A scheme of logic self repair including local interconnects. DDECS 2009: 8-11
- [c44]Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus: Reliability Estimation Process. DSD 2009: 221-224
- [c43]Tobias Koal, Heinrich Theodor Vierhaus, Daniel Scheit: A Concept for Logic Self Repair. DSD 2009: 621-624
- 2008
- [j9]René Kothe, Heinrich Theodor Vierhaus: A Scan Controller Concept for Low Power Scan Tests. J. Low Power Electronics 4(3): 420-428 (2008)
- [j8]Silvio Misera, Heinrich Theodor Vierhaus, André Sieber: Simulated fault injections and their acceleration in SystemC. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 270-278 (2008)
- [c42]Heinrich Theodor Vierhaus, René Kothe: Embedded Diagnostic Logic Test Exploiting Regularity. DSD 2008: 873-879
- [c41]Tobias Koal, Heinrich Theodor Vierhaus: Basic Architecture for Logic Self Repair. IOLTS 2008: 177-178
- 2007
- [c40]René Kothe, Heinrich Theodor Vierhaus: Flip-Flops and Scan-Path Elements for Nanoelectronics. DDECS 2007: 307-312
- [c39]Heinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera: Timing- / Power-Optimization for Digital Logic Based on Standard Cells. DSD 2007: 303-306
- [c38]Silvio Misera, Heinrich Theodor Vierhaus, André Sieber: Fault Injection Techniques and their Accelerated Simulation in SystemC. DSD 2007: 587-595
- [c37]R. Frost Brandenburg, D. Rudolph, Christian Galke, René Kothe, Heinrich Theodor Vierhaus: A Configurable Modular Test Processor and Scan Controller Architecture. IOLTS 2007: 277-284
- 2006
- [c36]Christian Galke, René Kothe, Heinrich Theodor Vierhaus: Logic Self Repair. ARCS Workshops 2006: 36-44
- [c35]Udo Krautz, Matthias Pflanz, Christian Jacobi, Hans-Werner Tast, Kai Weber, Heinrich Theodor Vierhaus: Evaluating coverage of error detection logic for soft errors using formal methods. DATE 2006: 176-181
- [c34]René Kothe, Christian Galke, S. Schultke, H. Froeschke, S. Gaede, Heinrich Theodor Vierhaus: Hardware/Software Based Hierarchical Self Test for SoCs. DDECS 2006: 159-160
- [c33]René Kothe, Heinrich Theodor Vierhaus, Torsten Coym, Wolfgang Vermeiren, Bernd Straube: Embedded Self Repair by Transistor and Gate Level Reconfiguration. DDECS 2006: 210-215
- [c32]Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber: A Mixed Language Fault Simulation of VHDL and SystemC. DSD 2006: 275-279
- [c31]Christian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus: Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes. DSD 2006: 433-438
- [c30]Christian Galke, René Kothe, S. Schultke, K. Winkler, J. Honko, Heinrich Theodor Vierhaus: Embedded Scan Test with Diagnostic Features for Self-Testing SoCs. IOLTS 2006: 181-182
- [c29]S. Habermann, René Kothe, Heinrich Theodor Vierhaus: Built-in Self Repair by Reconfiguration of FPGAs. IOLTS 2006: 187-188
- [c28]Axel Vick, Helmut Rossmann, Heinrich Theodor Vierhaus: Timing-/Power-getriebener Layout-Entwurf für Zellen-basierte Digitalschaltungen. MBMV 2006: 61-68
- 2005
- [c27]Heinrich Theodor Vierhaus, Helmut Rossmann: Power-/Timing - Optimierung für Zellen-basierte Digitalschaltungen in Submikron-Technologien. GI Jahrestagung (1) 2005: 339-343
- [c26]René Kothe, Christian Galke, Heinrich Theodor Vierhaus: A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. IOLTS 2005: 241-246
- [c25]Marcin Gomulkiewicz, Miroslaw Kutylowski, Heinrich Theodor Vierhaus, Pawel Wlaz: Synchronization Fault Cryptanalysis for Breaking A5/1. WEA 2005: 415-427
- 2004
- [c24]Claudia Kretzschmar, Christian Galke, Heinrich Theodor Vierhaus: A Hierarchical Self Test Scheme for SoCs. IOLTS 2004: 37-44
- [c23]Silvio Misera, Heinrich Theodor Vierhaus: FIT - A Parallel Hierarchical Fault Simulation Environment. PARELEC 2004: 289-294
- 2003
- [j7]Matthias Pflanz, K. Walther, Christian Galke, Heinrich Theodor Vierhaus: On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check. J. Electronic Testing 19(5): 501-510 (2003)
- [c22]Matthias Pflanz, Heinrich Theodor Vierhaus: Control Signal Protection For High Performance Processors. IOLTS 2003: 173-
- [c21]Christian Galke, Marcus Grabow, Heinrich Theodor Vierhaus: Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip. IOLTS 2003: 183-
- 2002
- [c20]Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus: A Test Processor Concept for Systems-on-a-Chip. ICCD 2002: 210-
- [c19]Matthias Pflanz, K. Walther, Christian Galke, Heinrich Theodor Vierhaus: On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check. IOLTW 2002: 69-73
- [c18]Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus: On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures. IOLTW 2002: 178
- 2001
- [j6]Matthias Pflanz, Heinrich Theodor Vierhaus: Online Check and Recovery Techniques for Dependable Embedded Processors. IEEE Micro 21(5): 24-40 (2001)
- [c17]C. Rousselle, Matthias Pflanz, A. Behling, T. Mohaupt, Heinrich Theodor Vierhaus: A register-transfer-level fault simulator for permanent and transient faults in embedded processors. DATE 2001: 811
- [c16]Matthias Pflanz, K. Walther, Heinrich Theodor Vierhaus: On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity. IOLTW 2001: 51-53
- 2000
- [c15]Matthias Pflanz, Christian Galke, Heinrich Theodor Vierhaus: A new method for on-line state machine observation for embedded microprocessors. HLDVT 2000: 34-39
1990 – 1999
- 1999
- [j5]Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante: SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 191-202 (1999)
- [c14]Matthias Pflanz, Heinrich Theodor Vierhaus, F. Pompsch: An efficient on-line-test and back-up scheme for embedded processors. ITC 1999: 964-972
- 1997
- [j4]Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano: Partitioning and analysis of static digital CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1292-1310 (1997)
- [c13]H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus: An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation. Great Lakes Symposium on VLSI 1997: 112-117
- [c12]H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus: A Parallel Approach Solving the Test Generation Problem for Synchronous Sequential Circuits. PARCO 1997: 549-556
- 1996
- [j3]Uwe Gläser, Heinrich Theodor Vierhaus: Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 410-423 (1996)
- [c11]Jörg Wilberg, A. Kuth, Raul Camposano, Wolfgang Rosenstiel, Heinrich Theodor Vierhaus: A Design Exploration Environment. Great Lakes Symposium on VLSI 1996: 77-80
- [c10]H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus: Automatic Test Pattern Generation with Optimal Load Balancing. PVM 1996: 205-212
- 1995
- [c9]Uwe Gläser, Heinrich Theodor Vierhaus: FOGBUSTER: an efficient algorithm for sequential test generation. EURO-DAC 1995: 230-235
- [c8]Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus: Improving topological ATPG with symbolic techniques. VTS 1995: 338-343
- 1994
- [c7]Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus: Local microcode generation in system design. Code Generation for Embedded Processors 1994: 171-187
- [c6]Uwe Gläser, Heinrich Theodor Vierhaus, M. Kley, A. Wiederhold: Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation. ICCAD 1994: 36-39
- [c5]R. Wolber, Uwe Gläser, Heinrich Theodor Vierhaus: Testability Analysis for Test Generation in Synchronous Sequential Circuits. ICCD 1994: 350-353
- 1993
- [j2]Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser, Raul Camposano: Fault behavior and testability of asynchronous CMOS circuits. Microprocessing and Microprogramming 38(1-5): 223-228 (1993)
- [c4]Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser: CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects. ITC 1993: 83-91
- 1992
- [j1]Uwe Hübner, Wolfgang Meyer, Heinrich Theodor Vierhaus: CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents. Microprocessing and Microprogramming 35(1-5): 377-382 (1992)
- [c3]Uwe Hübner, Heinrich Theodor Vierhaus: Efficient partitioning and analysis of digital CMOS-circuits. ICCAD 1992: 280-283
- [c2]Ursula Westerholz, Heinrich Theodor Vierhaus: Library Mapping of CMOS-Switch-Level-Circuits by Extraction of Isomorphic Subgraphs. ICCD 1992: 472-475
- [c1]Uwe Gläser, Uwe Hübner, Heinrich Theodor Vierhaus: Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects. ITC 1992: 21-29
Coauthor Index
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last updated on 2013-05-27 22:24 CEST by the dblp team