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T. N. Vijaykumar
2010 – today
- 2013
[c56]Syed Ali Raza Jafri, Gwendolyn Voskuilen, T. N. Vijaykumar: Wait-n-GoTM: improving HTM performance by serializing cyclic dependencies. ASPLOS 2013: 521-534- 2012
- [j13]Paolo Faraboschi, T. N. Vijaykumar: Top Picks from the 2011 Computer Architecture Conferences. IEEE Micro 32(3): 3-6 (2012)
- [c55]Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan, T. N. Vijaykumar: Tarazu: optimizing MapReduce on heterogeneous clusters. ASPLOS 2012: 61-74
- [c54]Balajee Vamanan, Jahangir Hasan, T. N. Vijaykumar: Deadline-aware datacenter tcp (D2TCP). SIGCOMM 2012: 115-126
- 2011
- [c53]Balajee Vamanan, T. N. Vijaykumar: TreeCAM: decoupling updates and lookups in packet classification. CoNEXT 2011: 27
- 2010
- [c52]Faraz Ahmad, T. N. Vijaykumar: Joint optimization of idle and cooling power in data centers while maintaining response time. ASPLOS 2010: 243-256
- [c51]Syed Ali Raza Jafri, Mithuna Thottethodi, T. N. Vijaykumar: LiteTM: Reducing transactional state overhead. HPCA 2010: 1-12
- [c50]Gwendolyn Voskuilen, Faraz Ahmad, T. N. Vijaykumar: Timetraveler: exploiting acyclic races for optimizing memory race recording. ISCA 2010: 198-209
- [c49]Syed Ali Raza Jafri, Yu-Ju Hong, Mithuna Thottethodi, T. N. Vijaykumar: Adaptive Flow Control for Robust Performance and Energy. MICRO 2010: 433-444
- [c48]Balajee Vamanan, Gwendolyn Voskuilen, T. N. Vijaykumar: EffiCuts: optimizing packet classification for memory and throughput. SIGCOMM 2010: 207-218
2000 – 2009
- 2008
- [j12]Zeshan Chishti, T. N. Vijaykumar: Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies. IEEE Trans. Computers 57(1): 69-81 (2008)
- [c47]Eric Chun, Zeshan Chishti, T. N. Vijaykumar: Shapeshifter: Dynamically changing pipeline width and speed to address process variations. MICRO 2008: 411-422
- [c46]Ahmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar, Steven Wereley, Stephen C. Jacobson: Automatic volume management for programmable microfluidics. PLDI 2008: 56-67
- 2007
- [c45]Ethan Schuchman, T. N. Vijaykumar: BlackJack: Hard Error Detection with Redundant Threads on SMT. DSN 2007: 327-337
- [c44]Ahmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar, Steven Wereley, Stephen C. Jacobson: Aquacore: a programmable architecture for microfluidics. ISCA 2007: 254-265
- [c43]Michael D. Powell, T. N. Vijaykumar: Resource area dilation to reduce power density in throughput servers. ISLPED 2007: 268-273
- [c42]Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar: Speculative thread decomposition through empirical optimization. PPOPP 2007: 205-214
- 2006
- [j11]Alan Fern, Robert Givan, Babak Falsafi, T. N. Vijaykumar: Dynamic feature selection for hardware prediction. Journal of Systems Architecture 52(4): 213-234 (2006)
- [j10]Mohamed A. Gomaa, T. N. Vijaykumar: Opportunistic Transient-Fault Detection. IEEE Micro 26(1): 92-99 (2006)
- [j9]Hilmi Ozdoganoglu, T. N. Vijaykumar, Carla E. Brodley, Benjamin A. Kuperman, Ankit Jalote: SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address. IEEE Trans. Computers 55(10): 1271-1285 (2006)
- [j8]Seon Wook Kim, Chong-liang Ooi, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar: Exploiting reference idempotency to reduce speculative storage overflow. ACM Trans. Program. Lang. Syst. 28(5): 942-965 (2006)
- [c41]Chen-Yong Cher, Il Park, T. N. Vijaykumar: Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?. ARCS 2006: 232-251
- [c40]Ethan Schuchman, T. N. Vijaykumar: A program transformation and architecture support for quantum uncomputation. ASPLOS 2006: 252-263
- [c39]Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Saurabh Bagchi: Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection. ICCD 2006
- 2005
- [j7]Benjamin A. Kuperman, Carla E. Brodley, Hilmi Ozdoganoglu, T. N. Vijaykumar, Ankit Jalote: Detection and prevention of stack buffer overflow attacks. Commun. ACM 48(11): 50-56 (2005)
- [j6]Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar: Combined circuit and architectural level variable supply-voltage scaling for low power. IEEE Trans. VLSI Syst. 13(5): 564-576 (2005)
- [c38]Jahangir Hasan, Ankit Jalote, T. N. Vijaykumar, Carla E. Brodley: Heat Stroke: Power-Density-Based Denial of Service in SMT. HPCA 2005: 166-177
- [c37]Ethan Schuchman, T. N. Vijaykumar: Rescue: A Microarchitecture for Testability and Defect Tolerance. ISCA 2005: 160-171
- [c36]
- [c35]Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar: Optimizing Replication, Communication, and Capacity Allocation in CMPs. ISCA 2005: 357-368
- [c34]Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar: Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. MICRO 2005: 294-304
- [c33]Jahangir Hasan, T. N. Vijaykumar: Dynamic pipelining: making IP-lookup truly scalable. SIGCOMM 2005: 205-216
- [e4]Babak Falsafi, T. N. Vijaykumar (Eds.): Power-Aware Computer Systems, 4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers. Lecture Notes in Computer Science 3471, Springer 2005, ISBN 3-540-29790-1
- 2004
- [j5]Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar: DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. VLSI Syst. 12(3): 245-254 (2004)
- [c32]Chen-Yong Cher, Antony L. Hosking, T. N. Vijaykumar: Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign. ASPLOS 2004: 199-210
- [c31]Mohamed A. Gomaa, Michael D. Powell, T. N. Vijaykumar: Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. ASPLOS 2004: 260-270
- [c30]T. N. Vijaykumar, Zeshan Chishti: Wire Delay is Not a Problem for SMT (In the Near Future). ISCA 2004: 40-51
- [c29]Michael D. Powell, T. N. Vijaykumar: Exploiting Resonant Behavior to Reduce Inductive Noise. ISCA 2004: 288-301
- [c28]Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar: Min-cut program decomposition for thread-level speculation. PLDI 2004: 59-70
- [e3]Babak Falsafi, T. N. Vijaykumar (Eds.): Power-Aware Computer Systems, Third International Workshop, PACS 2003, SanDiego, CA, USA, December 1, 2003, Revised Papers. Lecture Notes in Computer Science 3164, Springer 2004, ISBN 3-540-24031-4
- 2003
- [j4]Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz: Transient-Fault Recovery for Chip Multiprocessors. IEEE Micro 23(6): 76-83 (2003)
- [c27]Amit Agarwal, Kaushik Roy, T. N. Vijaykumar: Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. DATE 2003: 10778-10783
- [c26]Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy: Deterministic Clock Gating for Microprocessor Power Reduction. HPCA 2003: 113-122
- [c25]
- [c24]Michael D. Powell, T. N. Vijaykumar: Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. ISCA 2003: 72-83
- [c23]Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar: Transient-Fault Recovery for Chip Multiprocessors. ISCA 2003: 98-109
- [c22]Jahangir Hasan, Satish Chandra, T. N. Vijaykumar: Efficient Use of Memory Bandwidth to Improve Network Processor Throughput. ISCA 2003: 300-311
- [c21]Michael D. Powell, T. N. Vijaykumar: Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. ISLPED 2003: 223-228
- [c20]Praveen Dongara, T. N. Vijaykumar: Accelerating private-key cryptography via multithreading on symmetric multiprocessors. ISPASS 2003: 58-69
- [c19]Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy: VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. MICRO 2003: 19-28
- [c18]Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar: Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. MICRO 2003: 55-66
- [c17]Il Park, Chong-liang Ooi, T. N. Vijaykumar: Reducing Design Complexity of the Load/Store Queue. MICRO 2003: 411-422
- [e2]Babak Falsafi, T. N. Vijaykumar (Eds.): Power-Aware Computer Systems, Second International Workshop, PACS 2002 Cambridge, MA, USA, February 2, 2002, Revised Papers. Lecture Notes in Computer Science 2325, Springer 2003, ISBN 3-540-01028-9
- 2002
- [c16]Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar: Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. HPCA 2002: 151-161
- [c15]T. N. Vijaykumar, Irith Pomeranz, Karl Cheng: Transient-Fault Recovery Using Simultaneous Multithreading. ISCA 2002: 87-98
- [c14]Il Park, Michael D. Powell, T. N. Vijaykumar: Reducing register ports for higher speed and lower energy. MICRO 2002: 171-182
- 2001
- [j3]T. N. Vijaykumar, Sridhar Gopal, James E. Smith, Gurindar S. Sohi: Speculative Versioning Cache. IEEE Trans. Parallel Distrib. Syst. 12(12): 1305-1317 (2001)
- [j2]Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar: Reducing leakage in a high-performance deep-submicron instruction cache. IEEE Trans. VLSI Syst. 9(1): 77-89 (2001)
- [c13]
- [c12]Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar: An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. HPCA 2001: 147-157
- [c11]Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar: Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor. ICS 2001: 368-380
- [c10]Chen-Yong Cher, T. N. Vijaykumar: Skipper: a microarchitecture for exploiting control-flow independence. MICRO 2001: 4-15
- [c9]Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy: Reducing set-associative cache energy via way-prediction and selective direct-mapping. MICRO 2001: 54-65
- [c8]Seon Wook Kim, Chong-liang Ooi, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar: Reference idempotency analysis: a framework for optimizing speculative execution. PPOPP 2001: 2-11
- [e1]Babak Falsafi, T. N. Vijaykumar (Eds.): Power-Aware Computer Systems, First International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers. Lecture Notes in Computer Science 2008, Springer 2001, ISBN 3-540-42329-X
1990 – 1999
- 1999
- [j1]T. N. Vijaykumar, Gurindar S. Sohi: Task Selection for the Multiscalar Architecture. J. Parallel Distrib. Comput. 58(2): 132-158 (1999)
- [c7]
- 1998
- [c6]Sridhar Gopal, T. N. Vijaykumar, James E. Smith, Gurindar S. Sohi: Speculative Versioning Cache. HPCA 1998: 195-205
- [c5]Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar: Multiscalar Processors. 25 Years ISCA: Retrospectives and Reprints 1998: 521-532
- [c4]
- 1997
- [c3]Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi: Dynamic Speculation and Synchronization of Data Dependences. ISCA 1997: 181-193
- 1995
- [c2]
- 1994
- [c1]Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi: The anatomy of the register file in a multiscalar processor. MICRO 1994: 181-190
Coauthor Index
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last updated on 2013-03-17 18:59 CET by the dblp team