Julio Villalba

Julio Villalba-Moreno

	2012
j14		Julio Villalba, Tomás Lang, Javier Hormigo: Radix-2 Multioperand and Multiformat Streaming Online Addition. IEEE Trans. Computers 61(6): 790-803 (2012)
j13		Álvaro Vázquez, Julio Villalba-Moreno, Elisardo Antelo, Emilio L. Zapata: Redundant Floating-Point Decimal CORDIC Algorithm. IEEE Trans. Computers 61(11): 1551-1562 (2012)
c25		Carlos Garcia-Vega, Sonia Gonzalez-Navarro, Julio Villalba-Moreno, Emilio L. Zapata: On-line Decimal Adder with RBCD Representation. ASAP 2012: 53-60
	2011
j12		Francisco J. Jaime, M. A. Sánchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata: High-Speed Algorithms and Architectures for Range Reduction Computation. IEEE Trans. VLSI Syst. 19(3): 512-516 (2011)
	2010
j11		Francisco J. Jaime, Miguel A. Sanchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata: Enhanced Scaling-Free CORDIC. IEEE Trans. on Circuits and Systems 57-I(7): 1654-1662 (2010)
c24		Francisco J. Quiles, Manuel Ortiz, María Brox, Carlos D. Moreno, Javier Hormigo, Julio Villalba: UCORE: Reconfigurable Platform for Educational Purposes. ReConFig 2010: 109-114
	2009
c23		Álvaro Vázquez, Julio Villalba, Elisardo Antelo: Computation of Decimal Transcendental Functions Using the CORDIC Algorithm. IEEE Symposium on Computer Arithmetic 2009: 179-186
c22		Javier Hormigo, Manuel Ortiz, Francisco J. Quiles, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata: Efficient Implementation of Carry-Save Adders in FPGAs. ASAP 2009: 207-210
c21		Carlos D. Moreno, Francisco J. Quiles, Manuel Ortiz, María Brox, Javier Hormigo, Julio Villalba, Emilio L. Zapata: Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator. ICECS 2009: 419-422
	2008
j10		Elisardo Antelo, Julio Villalba, Emilio L. Zapata: A Low-Latency Pipelined 2D and 3D CORDIC Processors. IEEE Trans. Computers 57(3): 404-417 (2008)
j9		Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata: Pipelined Architecture for Additive Range Reduction. Signal Processing Systems 53(1-2): 103-112 (2008)
c20		Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata: SIMD Enhancements for a Hough Transform Implementation. DSD 2008: 899-903
c19		Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata: New SIMD instructions set for image processing applications enhancement. ICIP 2008: 1396-1399
	2007
c18		Julio Villalba, Javier Hormigo, Tomás Lang: Improving the Throughput of On-line Addition for Data Streams. ASAP 2007: 272-277
	2006
j8		Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides, Emilio L. Zapata: SAD computation based on online arithmetic for motion estimation. Microprocessors and Microsystems 30(5): 250-258 (2006)
j7		Julio Villalba, Tomás Lang, Mario A. González: Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations. IEEE Trans. Computers 55(3): 254-267 (2006)
c17		Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata: Pipelined Range Reduction for Floating Point Numbers. ASAP 2006: 145-152
c16		Joaquín Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata: Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. FPL 2006: 1-4
	2005
c15		Elisardo Antelo, Julio Villalba: Low Latency Pipelined Circular CORDIC. IEEE Symposium on Computer Arithmetic 2005: 280-287
c14		Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata: On-line Multioperand Addition Based on On-line Full Adders. ASAP 2005: 322-327
	2004
j6		Javier Hormigo, Julio Villalba, Emilio L. Zapata: CORDIC Processor for Variable-Precision Interval Arithmetic. VLSI Signal Processing 37(1): 21-39 (2004)
c13		Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides: Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. FPL 2004: 986-990
c12		Gerardo Bandera, Mario A. González, Julio Villalba, Javier Hormigo, Emilio L. Zapata: Evaluation of Elementary Functions Using Multimedia Features. IPDPS 2004
	2002
c11		Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata: Polynomial Evaluation on Multimedia Processors. ASAP 2002: 265-
	2000
c10		Javier Hormigo, Julio Villalba, Michael J. Schulte: A Hardware Algorithm for Variable-Precision Logarithm. ASAP 2000: 215-224
c9		Julio Villalba, Javier Hormigo, Mario A. González, Emilio L. Zapata: MMX-Like Architecture Extension to Support the Rotation Operation. IEEE International Conference on Multimedia and Expo (III) 2000: 1383-1386
	1999
c8		Javier Hormigo, Julio Villalba, Emilio L. Zapata: Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. IEEE Symposium on Computer Arithmetic 1999: 186-193
c7		Javier Hormigo, Julio Villalba, Emilio L. Zapata: Arithmetic Unit for the Computation of Interval Elementary Functions. EUROMICRO 1999: 1063-1066
	1998
j5		Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: Radix-4 Vectoring CORDIC Algorithm and Architectures. VLSI Signal Processing 19(2): 127-147 (1998)
j4		Julio Villalba, Tomás Lang, Emilio L. Zapata: Parallel Compensation of Scale Factor for the CORDIC Algorithm. VLSI Signal Processing 19(3): 227-241 (1998)
	1997
j3		Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata: High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers 46(8): 855-870 (1997)
c6		Julio Villalba, Tomás Lang: Low latency word serial CORDIC. ASAP 1997: 124-131
	1996
j2		Javier D. Bruguera, Nicolas Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata: Cordic based parallel/pipelined architecture for the Hough transform. VLSI Signal Processing 12(3): 207-221 (1996)
c5		Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP 1996: 55-64
c4		Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata: High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II 1996: 155-164
	1995
j1		Nicolas Guil, Julio Villalba, Emilio L. Zapata: A fast Hough transform for segment detection. IEEE Transactions on Image Processing 4(11): 1541-1548 (1995)
c3		Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata: Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic 1995: 172-179
c2		Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata: Digit On-line Large Radix CORDIC Rotator. ASAP 1995: 246-257
c1		Julio Villalba, J. A. Hidalgo, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP 1995: 258-269

Coauthor Index

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