Eugenio Villar

Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia: A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models. CODES+ISSS 2012: 529-538

Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia: The COMPLEX Eclipse framework for UML/MARTE specification and design space exploration of embedded systems. DASIP 2012: 1-2

Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia, Francisco Ferrero, Raúl Valencia: COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration. DSD 2012: 349-358

Fernando Herrera, Hector Posadas, Eugenio Villar, Daniel Calvo: Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE. DSD 2012: 692-699

Fernando Herrera, Pablo Peñil, Hector Posadas, Eugenio Villar: A model-driven methodology for the development of SystemC executable environments. FDL 2012: 177-184

Hector Posadas, Eugenio Villar, Dominique Ragot, Marcos Martínez: Early, time-approximate modeling of multi-OS. linux platforms in a systemC co-simulation environment. Comput. Syst. Sci. Eng. 26(6) (2011)

Daniel Calvo, Pablo González, Luis Diaz, Hector Posadas, Pablo Sánchez, Eugenio Villar, Andrea Acquaviva, Enrico Macii: A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design. J. Low Power Electronics 7(1): 2-16 (2011)

Hector Posadas, Luis Diaz, Eugenio Villar: Fast data-cache modeling for native co-simulation. ASP-DAC 2011: 425-430

Fernando Herrera, Eugenio Villar: A framework for the generation from UML/MARTE models of IPXACT HW platform descriptions for multi-level performance estimation. FDL 2011: 1-8

Fernando Herrera, Eugenio Villar, Philipp A. Hartmann: Systemc refinement of abstract adaptive processes for implementation into Dynamically Reconfigurable Hardware. FDL 2011: 1-8

Pablo Peñil, J. Medina, Hector Posadas, Eugenio Villar: Generating heterogeneous executable specifications in SystemC from UML/MARTE models. ISSE 6(1-2): 65-71 (2010)

Hector Posadas, Eugenio Villar: Modeling Separate Memory Spaces in Native Co-simulation with SystemC for Design Space Exploration. ARCS Workshops 2010: 313-318

Eugenio Villar, Fernando Herrera, Victor Fernández: Formal Support for Untimed SystemC Specifications: Application to High-level Synthesis. FDL 2010: 74-79

Pablo Peñil, Fernando Herrera, Eugenio Villar: Formal Foundations for MARTE-SystemC Interoperability. FDL 2010: 197-202

Juan Castillo, Hector Posadas, Eugenio Villar, Marcos Martínez: Fast instruction cache modeling for approximate timed HW/SW co-simulation. ACM Great Lakes Symposium on VLSI 2010: 191-196

Pablo Peñil, Hector Posadas, Eugenio Villar: Formal Modeling for UML/MARTE Concurrency Resources. ICECCS 2010: 343-348

Roberto Varona-Gomez, Eugenio Villar: AADS+: AADL Simulation Including the Behavioral Annex. ICECCS 2010: 379-384

Hector Posadas, Eugenio Villar, Dominique Ragot, Marcos Martínez: Early Modeling of Linux-Based RTOS Platforms in a SystemC Time-Approximate Co-simulation Environment. ISORC 2010: 238-244

Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Dongrui Fan, Zhang Hao, Shibin Tang: MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures. ISVLSI 2010: 488-493

Wolfgang Müller, Da He, Fabian Mischkalla, Arthur Wegele, Paul Whiston, Pablo Peñil, Eugenio Villar, Nikolaos Mitas, Dimitrios Kritharidis, Florent Azcarate, Manuel Carballeda: The SATURN Approach to SysML-Based HW/SW Codesign. ISVLSI 2010: 506-511

Sara Real, Hector Posadas, Eugenio Villar: L2 Cache Modeling based on address modification for Native Co-Simulation in SystemC. SIES 2010: 225-228

Fernando Herrera, Eugenio Villar: Local application of simulation directed for Exhaustive Coverage of Schedulings of SystemC specifications. FDL 2009: 1-6

Roberto Varona-Gomez, Eugenio Villar: AADL Simulation and Performance Analysis in SystemC. ICECCS 2009: 323-328

Hector Posadas, Eugenio Villar: Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulation. IESS 2009: 12-23

Markus Damm, Jan Haase, Christoph Grimm, Fernando Herrera, Eugenio Villar: Bridging MoCs in SystemC Specifications of Heterogeneous Systems. EURASIP J. Emb. Sys. 2008 (2008)

Christoph Grimm, Axel Jantsch, Sandeep Kumar Shukla, Eugenio Villar: C-Based Design of Heterogeneous Embedded Systems. EURASIP J. Emb. Sys. 2008 (2008)

Eugenio Villar, Axel Jantsch, Christoph Grimm, Tim Kogel: Heterogeneous System-level Specification Using SystemC. DATE 2008

Fernando Herrera, Eugenio Villar, Philipp A. Hartmann: Specification of Adaptive HW/SW Systems in SystemC. FDL 2008: 61-65

Fernando Herrera, Eugenio Villar: A framework for heterogeneous specification and design of electronic embedded systems in SystemC. ACM Trans. Design Autom. Electr. Syst. 12(3) (2007)

Fernando Herrera, Eugenio Villar, Christoph Grimm, Markus Damm, Jan Haase: A general approach to the interoperability of HetSC and SystemC-AMS. FDL 2007: 32-37

Hector Posadas, David Quijano, Eugenio Villar, Marcos Martínez: Protocol Bus Modeling using inheritance with TLM2.0. FDL 2007: 80-85

Andreas Herrholz, Frank Oppenheimer, Philipp A. Hartmann, Andreas Schallenberg, Wolfgang Nebel, Christoph Grimm, Markus Damm, Jan Haase, Florian Brame, Fernando Herrera, Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, Marcos Martínez: The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. FPL 2007: 396-401

Hector Posadas, Jesús Ádamez, Pablo Sánchez, Eugenio Villar, Francisco Blasco: POSIX modeling in SystemC. ASP-DAC 2006: 485-490

Fernando Herrera, Eugenio Villar: A framework for embedded system specification under different models of computation in SystemC. DAC 2006: 911-914

Fernando Herrera, Eugenio Villar: Extension of the SystemC Kernel for Simulation Coverage. FDL 2006: 161-168

Hector Posadas, Jesús Ádamez, Eugenio Villar, Francisco Blasco, F. Escuder: RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model. Design Autom. for Emb. Sys. 10(4): 209-227 (2005)

Fernando Herrera, Eugenio Villar: Mixing Synchronous Reactive and Untimed Models of Computation. FDL 2005: 315-329

Hector Posadas, Fernando Herrera, V. FernÁndez, Pablo Sánchez, Eugenio Villar, Francisco Blasco: Single Source Design Environment for Embedded Systems Based on SystemC. Design Autom. for Emb. Sys. 9(4): 293-312 (2004)

Hector Posadas, Fernando Herrera, Pablo Sánchez, Eugenio Villar, Francisco Blasco: System-Level Performance Analysis in SystemC. DATE 2004: 378-383

Fernando Herrera, Pablo Sánchez, Eugenio Villar: Heterogeneous System-Level Specification in SystemC. FDL 2004: 404-416

Fernando Herrera, Hector Posadas, Pablo Sánchez, Eugenio Villar: Systemic Embedded Software Generation from SystemC. DATE 2003: 10142-10149

Fernando Herrera, Pablo Sánchez, Eugenio Villar: Modeling of CSP, KPN and SR Systems with SystemC. FDL 2003: 572-583

Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, J. Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong: C/C++: progress or deadlock in system-level specification. DATE 2001: 136-137

Giulio Gorla, Eduard Moser, Wolfgang Nebel, Eugenio Villar: System Specification Experiments on a Common Benchmark. IEEE Design & Test of Computers 17(3): 22-32 (2000)

Adrian López, Maite Veiga, Eugenio Villar: Hardware/Software Embedded System Specifiaction and Design Using Ada and VHDL. Ada-Europe 1999: 356-370

Pedro Tabuenca, Pablo Sánchez, Eugenio Villar: An algorithm for clock cycle selection in behavioral synthesis. Journal of Systems Architecture 44(9-10): 773-786 (1998)

Masaharu Imai, Eugenio Villar: ASPDAC 1995: HDL synthesizability and interoperability. IEEE Design & Test of Computers 13(1): 3-4 (1996)

Manfred Selz, Wolfgang Ecker, Eugenio Villar: VHDL synthesis description portability: The need for Level synthesis subsets. Journal of Systems Architecture 42(2): 105-116 (1996)

Masaharu Imai, Eugenio Villar: Future direction of synthesizability and interoperability of HDL's: part 1. ASP-DAC 1995

Eugenio Villar, Masaharu Imai: Future direction of synthesizabilty and interoperability of HDL's: part 2. ASP-DAC 1995