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 | 2004 | |
|---|---|---|
| c33 |      | Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota: Combining dictionary coding and LFSR reseeding for test data compression. DAC 2004: 944-947 |
| 2003 | ||
| c32 | | Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota: Test Vector Generation Based on Correlation Model for Ratio-Iddq. ITC 2003: 545-554 |
| c31 | | Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota: Development of Energy Consumption Ratio Test. VTS 2003: 279-286 |
| 2002 | ||
| j15 | | Wanli Jiang, Bapiraju Vinnakota: Statistical threshold formulation for dynamic Idd test. IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 694-705 (2002) |
| 2001 | ||
| j14 | | Wanli Jiang, Bapiraju Vinnakota: Defect-oriented test scheduling. IEEE Trans. VLSI Syst. 9(3): 427-438 (2001) |
| c30 | | Xiaoyun Sun, Seonki Kim, Bapiraju Vinnakota: Crosstalk Fault Detection by Dynamic Idd. ICCAD 2001: 375- |
| c29 |  | Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller: High Performance Parallel Fault Simulation. ICCD 2001: 308-313 |
| c28 | | Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota: Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter. ISCAS (1) 2001: 552-555 |
| c27 | | |
| 2000 | ||
| j13 | | Wanli Jiang, Bapiraju Vinnakota: IC test using the energy consumption ratio. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 129-141 (2000) |
| j12 | | Bapiraju Vinnakota, Ramesh Harjani: DFT for digital detection of analog parametric faults in SC filters. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 789-798 (2000) |
| c26 | | Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota: Optimal test-set generation for parametric fault detection in switched capacitor filters. Asian Test Symposium 2000: 72-77 |
| c25 | | Seonki Kim, Bapiraju Vinnakota: Fast Test Application Technique Without Fast Scan Clocks. ICCAD 2000: 464-467 |
| c24 | | Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota: An analysis of the delay defect detection capability of the ECR test method. ITC 2000: 1060-1069 |
| c23 | | Bapiraju Vinnakota, André Ivanov: Biomedical ICs: What is Different about Testing those ICs? VTS 2000: 329-332 |
| 1999 | ||
| j11 | | Minesh B. Amin, Bapiraju Vinnakota: Data parallel fault simulation. IEEE Trans. VLSI Syst. 7(2): 183-190 (1999) |
| c22 | | Ramesh Harjani, Bapiraju Vinnakota: Digital Aetection of Analog Parametric Faults in SC Filters. DAC 1999: 772-777 |
| c21 | | |
| c20 | | Bapiraju Vinnakota: Deep submicron defect detection with the energy consumption ratio. ICCAD 1999: 467-470 |
| c19 | | Wanli Jiang, Bapiraju Vinnakota: Statistical threshold formulation for dynamic I_dd test. ITC 1999: 57-66 |
| c18 | | |
| 1998 | ||
| j10 | | Bapiraju Vinnakota, Jason Andrews: Fast fault translation. IEEE Trans. VLSI Syst. 6(1): 122-133 (1998) |
| c17 | | |
| c16 | | Bapiraju Vinnakota, Wanli Jiang, Dechang Sun: Process-tolerant test with energy consumption ratio. ITC 1998: 1027-1036 |
| 1997 | ||
| j9 | | Minesh B. Amin, Bapiraju Vinnakota: Workload Distribution in Fault Simulation. J. Electronic Testing 10(3): 277-282 (1997) |
| j8 | | Bapiraju Vinnakota: Monitoring Power Dissipation for Fault Detection. J. Electronic Testing 11(2): 173-181 (1997) |
| c15 | | Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi: Pseudoduplication - An ACOB Technique for Single-Ended Circuits. VLSI Design 1997: 398-402 |
| 1996 | ||
| c14 | | Minesh B. Amin, Bapiraju Vinnakota: Zamlog: a parallel algorithm for fault simulation based on Zambezi. ICCAD 1996: 509-512 |
| c13 | | |
| c12 | | Minesh B. Amin, Bapiraju Vinnakota: ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator. VTS 1996: 438-443 |
| c11 | | |
| 1995 | ||
| j7 | | Bapiraju Vinnakota: Implementing Multiplication with Split Read-Only Memory. IEEE Trans. Computers 44(11): 1352-1356 (1995) |
| c10 | | Bapiraju Vinnakota, Ramesh Harjani, Nicholas J. Stessman: System-Level Design for Test of Fully Differential Analog Circuits. DAC 1995: 450-454 |
| c9 | | |
| c8 | | Bapiraju Vinnakota, Nicholas J. Stessman: Reducing test application time in scan design schemes. VTS 1995: 367-373 |
| 1994 | ||
| j6 | | Bapiraju Vinnakota, V. V. Bapeswara Rao: Enumeration of Binary Trees. Inf. Process. Lett. 51(3): 125-127 (1994) |
| j5 | | Bapiraju Vinnakota, V. V. Bapeswara Rao: Generation of All Reed-Muller Expansions of a Switching Function. IEEE Trans. Computers 43(1): 122-124 (1994) |
| j4 | | Bapiraju Vinnakota, Niraj K. Jha: Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. IEEE Trans. Parallel Distrib. Syst. 5(10): 1099-1106 (1994) |
| j3 | | Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi: A C-testable carry-free divider. IEEE Trans. VLSI Syst. 2(4): 472-488 (1994) |
| c7 | | Bapiraju Vinnakota, Jason Andrews: Functional Test Generation for FSMs by Fault Extraction. DAC 1994: 712-715 |
| c6 | | Bapiraju Vinnakota, Ramesh Harjani: The Design of Analog Self-Checking Circuits. VLSI Design 1994: 67-70 |
| c5 | | |
| 1993 | ||
| j2 | | Bapiraju Vinnakota, Niraj K. Jha: Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems. IEEE Trans. Computers 42(8): 924-937 (1993) |
| j1 | | Bapiraju Vinnakota, Niraj K. Jha: Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs. IEEE Trans. Parallel Distrib. Syst. 4(8): 864-874 (1993) |
| c4 | | Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi: A C-Testable Carry-Free Divider. ICCD 1993: 206-213 |
| 1992 | ||
| c3 | | |
| 1991 | ||
| c2 | | Bapiraju Vinnakota, Niraj K. Jha: Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. FTCS 1991: 504-511 |
| 1990 | ||
| c1 | | Bapiraju Vinnakota, Niraj K. Jha: A dependence graph-based approach to the design of algorithm-based fault tolerant systems. FTCS 1990: 122-129 |
Colors in the list of coauthors
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