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Chandramouli Visweswariah
2000 – 2009
- 2006
[j7]Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, Jeff Piaget, Natesan Venkateswaran, Jeffrey G. Hemmett: First-Order Incremental Block-Based Statistical Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2170-2180 (2006)- [j6]Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah: Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2376-2392 (2006)
- 2005
- [j5]Andreas Wächter, Chandramouli Visweswariah, Andrew R. Conn: Large-scale nonlinear optimization in circuit tuning. Future Generation Comp. Syst. 21(8): 1251-1262 (2005)
- 2004
- [c16]Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan: First-order incremental block-based statistical timing analysis. DAC 2004: 331-336
- [c15]Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah: Is statistical timing statistically significant? DAC 2004: 498
- 2003
- [c14]Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah: Statistical timing for parametric yield prediction of digital integrated circuits. DAC 2003: 932-937
- 2002
- [c13]Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski: Uncertainty-aware circuit optimization. DAC 2002: 58-63
- 2001
- [c12]Andrew R. Conn, Chandramouli Visweswariah: Overview of continuous optimization advances and applications to circuit tuning. ISPD 2001: 74-81
- 2000
- [j4]Chandramouli Visweswariah, Ruud A. Haring, Andrew R. Conn: Noise considerations in circuit optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 679-690 (2000)
1990 – 1999
- 1999
- [c11]Andrew R. Conn, Ibrahim M. Elfadel, W. W. Molzen, P. R. O'Brien, Philip N. Strenski, Chandramouli Visweswariah, C. B. Whan: Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation. DAC 1999: 452-459
- [c10]Chandramouli Visweswariah, Andrew R. Conn: Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation. ICCAD 1999: 244-252
- 1998
- [j3]Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu: JiffyTune: circuit optimization using time-domain sensitivities. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1292-1309 (1998)
- [c9]Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah: Noise considerations in circuit optimization. ICCAD 1998: 220-227
- 1997
- [c8]Chandramouli Visweswariah: Optimization techniques for high-performance digital circuits. ICCAD 1997: 198-205
- [c7]Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah, Chai Wah Wu: Circuit optimization via adjoint Lagrangians. ICCAD 1997: 281-288
- 1996
- [c6]Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah: Optimization of custom MOS circuits by transistor sizing. ICCAD 1996: 174-180
- [c5]Daniel Brand, Chandramouli Visweswariah: Inaccuracies in power estimation during logic synthesis. ICCAD 1996: 388-394
- 1993
- [c4]Chandramouli Visweswariah, Jalal A. Wehbeh: Incremental Event-Driven Simulation of Digital FET Circuits. DAC 1993: 737-741
- 1992
- [j2]Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen: M3-a multilevel mixed-mode mixed A/D simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 575-585 (1992)
- 1991
- [j1]Chandramouli Visweswariah, Ronald A. Rohrer: Piecewise approximate circuit simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 861-870 (1991)
- [c3]Chandramouli Visweswariah, Ronald A. Rohrer: Efficient Simulation of Bipolar Digital ICs. DAC 1991: 32-37
- 1990
- [c2]Chandramouli Visweswariah, Peter Feldmann, Ronald A. Rohrer: Incorporation of Inductors in Piecewise Approximate Circuit Simulation. ICCAD 1990: 162-165
1980 – 1989
- 1988
- [c1]Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen: Model Development and Verification for High Level Analog Blocks. DAC 1988: 376-382
Coauthor Index
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last updated on 2013-05-28 21:39 CEST by the dblp team