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Mircea Vladutiu
2010 – today
- 2012
[b1]Mircea Vladutiu: Computer Arithmetic - Algorithms and Hardware Implementations. Springer 2012, ISBN 978-3-642-18314-0, pp. I-VI, 1-267- [j5]Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Simulated fault injection methodology for gate-level quantum circuit reliability assessment. Simulation Modelling Practice and Theory 23: 60-70 (2012)
- [c42]Septimiu Fabian Mare, Mircea Vladutiu, Lucian Prodan: High capacity steganographic algorithm based on payload adaptation and optimization. SACI 2012: 87-92
- [c41]Patrik Emanuel Mezö, Mircea Vladutiu, Lucian Prodan: HMail: A hybrid mailing system based on the collaboration between traditional and Peer-to-Peer mailing architectures. SACI 2012: 255-260
- [c40]Liviu Agnola, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan: Simplified selective fault tolerance technique for protection of selected inputs via triple modular redundancy systems. SACI 2012: 267-272
- 2011
- [c39]Septimiu Fabian Mare, Mircea Vladutiu, Lucian Prodan: Decreasing Change Impact Using Smart LSB Pixel Mapping and Data Rearrangement. CIT 2011: 269-276
- [c38]Patrik Emanuel Mezö, Mircea Vladutiu, Lucian Prodan: Design of a Hierarchical Based DHT Overlay P2P Routing Algorithm. CIT 2011: 415-420
- [c37]Liviu Agnola, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan: Improving performance of robust Self Adaptive Caches by optimizing the switching algorithm. DDECS 2011: 297-300
- 2010
- [j4]Oana Boncalo, Alexandru Amaricai, Mihai Udrescu, Mircea Vladutiu: Quantum circuit's reliability assessment with VHDL-based simulated fault injection. Microelectronics Reliability 50(2): 304-311 (2010)
- [j3]Alexandru Amaricai, Mircea Vladutiu, Oana Boncalo: Design Issues and Implementations for Floating-Point Divide-Add Fused. IEEE Trans. on Circuits and Systems 57-II(4): 295-299 (2010)
- [c36]Flavius Opritoiu, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan: Concurrent Error Detection for Multiplicative Inversion of Advanced Encryption Standard. CIT 2010: 582-588
- [c35]Flavius Opritoiu, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu: A high-speed AES architecture implementation. Conf. Computing Frontiers 2010: 95-96
- [c34]Liviu Agnola, Mircea Vladutiu, Mihai Udrescu: Self-Adaptive mechanism for cache memory reliability improvement. DDECS 2010: 117-118
- [c33]Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Performance Analysis for Genetic Quantum Circuit Synthesis. ICAISC (2) 2010: 205-212
- [c32]Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Adaptive vs. Self-adaptive Parameters for Evolving Quantum Circuits. ICES 2010: 348-359
2000 – 2009
- 2009
- [c31]Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Genetic algorithm based quantum circuit synthesis with adaptive parameters control. IEEE Congress on Evolutionary Computation 2009: 896-903
- [c30]Flavius Opritoiu, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan: Round-level concurrent error detection applied to Advanced Encryption Standard. DDECS 2009: 270-275
- [c29]Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Quantum Circuit Synthesis with Adaptive Parameters Control. EuroGP 2009: 339-350
- [c28]Razvan Bogdan, Mircea Vladutiu: Intrusions Detection in Intelligent Agent-Based Non-traditional Grids. ICETC 2009: 116-121
- [c27]Flavius Opritoiu, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu: Built-in self test applicability for the non-linear operations of Advanced Encryption Standard. SACI 2009: 307-312
- 2008
- [c26]Alexandru Amaricai, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan, Oana Boncalo: Floating point multiplication rounding schemes for interval arithmetic. ASAP 2008: 19-24
- [c25]Virgil E. Petcu, Alexandru Amaricai, Mircea Vladutiu: A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units. DDECS 2008: 146-149
- [c24]Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: Fault-Tolerant Memory Design and Partitioning Issues in Embryonics. ICES 2008: 372-381
- [c23]Versavia Ancusa, Razvan Bogdan, Mircea Vladutiu: Discussing Redundancy Issues in Intelligent Agent-Based Non-traditional Grids. KES (2) 2008: 297-305
- [c22]Versavia Ancusa, Razvan Bogdan, Mircea Vladutiu: Redundancy at Link Level for Non-Traditional Grids Implemented with Intelligent Agents. NCM (1) 2008: 597-603
- 2007
- [j2]Lucian Prodan, Mihai Udrescu, Oana Boncalo, Mircea Vladutiu: Design for dependability in emerging technologies. JETC 3(2) (2007)
- [c21]Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai: Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits. Annual Simulation Symposium 2007: 213-220
- [c20]Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo: Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor. DDECS 2007: 223-226
- [c19]Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo: Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition. DSD 2007: 132-137
- [c18]Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai: Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment. DSD 2007: 634-640
- [c17]Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Automatic Synthesis for Quantum Circuits Using Genetic Algorithms. ICANNGA (1) 2007: 174-183
- [c16]Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai: Simulated Fault Injection for Quantum Circuits Based on Simulator Commands. SACI 2007: 245-250
- [p1]Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: A Genetic Algorithm Framework Applied to Quantum Circuit Synthesis. NICSO 2007: 419-429
- 2006
- [c15]Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Implementing quantum genetic algorithms: a solution based on Grover's algorithm. Conf. Computing Frontiers 2006: 71-82
- [c14]Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: A dependability perspective on emerging technologies. Conf. Computing Frontiers 2006: 187-198
- 2005
- [c13]Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: The Bubble Bit Technique as Improvement of HDL-Based Quantum Circuits Simulation. Annual Simulation Symposium 2005: 217-224
- [c12]Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Improving quantum circuit dependability with reconfigurable quantum gate arrays. Conf. Computing Frontiers 2005: 133-144
- [c11]Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: Reliability assessment in embryonics inspired by fault-tolerant quantum computation. Conf. Computing Frontiers 2005: 323-333
- [c10]Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: Survivability of Embryonic Memories: Analysis and Design Principles. Evolvable Hardware 2005: 280-289
- [c9]Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: Multiple-level concatenated coding in embryonics: a dependability analysis. GECCO 2005: 941-948
- 2004
- [j1]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints. J. Electronic Testing 20(1): 61-78 (2004)
- [c8]Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation. Conf. Computing Frontiers 2004: 96-110
- [c7]Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: Self-Repairing Embryonic Memory Arrays. Evolvable Hardware 2004: 130-137
- 2001
- [c6]V. Muresan, Xiaojun Wang, Mircea Vladutiu: A combined tree growing technique for block-test scheduling under power constraints. ISCAS (5) 2001: 255-258
- [c5]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints. IEEE International Workshop on Rapid System Prototyping 2001: 162-167
- 2000
- [c4]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. Asian Test Symposium 2000: 465-470
- [c3]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: A comparison of classical scheduling approaches in power-constrained block-test scheduling. ITC 2000: 882-891
- [c2]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: Power-Constrained Block-Test List Scheduling. IEEE International Workshop on Rapid System Prototyping 2000: 182-187
- [c1]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints. VTS 2000: 417-422
Coauthor Index
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last updated on 2012-12-11 20:07 CET by the dblp team