Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
M. E. Waite
1990 – 1999
- 1996
[c6]F. Z. Ieromnimon, T. J. Reynolds, M. E. Waite: The Design and Simulation of the PACE Prototype Architecture. MASCOTS 1996: 157-161
[c5]M. E. Waite, T. J. Reynolds, F. Z. Ieromnimon: Parallel Graph Reduction with the PACE Architecture. PDP 1996: 448-454- 1995
[c4]T. J. Reynolds, M. E. Waite, F. Z. Ieromnimon: PACE: Fine-Grained Parallel Graph Reducion. ICPP (1) 1995: 15-18
[c3]M. E. Waite, T. J. Reynolds, F. Z. Ieromnimon: A New Approach to the Design of a Highly-Parallel Computer. Parallel and Distributed Computing and Systems 1995: 451-454- 1992
[c2]Simon H. Lavington, M. E. Waite, Jerome Robinson, Neil Dewhurst: Exploiting Parallelism in Primitive Operations on Bulk Data Types. PARLE 1992: 893-908
1980 – 1989
- 1987
[c1]Simon H. Lavington, M. Standing, Y. J. Jiang, C. J. Wang, M. E. Waite: Hardware Memory Management for Large Knowledge Bases. PARLE (1) 1987: 226-241
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2012-12-02 21:47 CET by the dblp team



