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Shin'ichi Wakabayashi
2010 – today
- 2011
[c30]Satoru Nakano, Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi: A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations. DSD 2011: 701-707- [c29]Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama: An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators. FPL 2011: 157-161
- 2010
- [c28]Yuichiro Utan, Shin'ichi Wakabayashi, Shinobu Nagayama: An FPGA-based text search engine for approximate regular expression matching. FPT 2010: 184-191
2000 – 2009
- 2009
- [c27]Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama: A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular Set. ERSA 2009: 151-157
- 2008
- [c26]Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama: A systolic regular expression pattern matching engine and its application to network intrusion detection. FPT 2008: 297-300
- 2007
- [c25]Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama: A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA Implementation. FPT 2007: 261-264
- [c24]Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama: A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning. PDPTA 2007: 801-807
- 2006
- [c23]Shin'ichi Wakabayashi, Yoshihiro Kimura, Shinobu Nagayama: FPGA implementation of tabu search for the quadratic assignment problem. FPT 2006: 269-272
- [c22]Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A Decision Method of Attribute Importance for Classification by Outlier Detection. ICDE Workshops 2006: 120
- 2005
- [c21]Shin'ichi Wakabayashi, Kenji Kikuchi: Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAs. FPT 2005: 69-76
- [c20]Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida: Feature Extraction of Clusters Based on FlexDice. ICDE Workshops 2005: 1126
- [c19]Takeshi Fushimi, Yoko Kamidoi, Shin'ichi Wakabayashi: An Algorithm for Computing Global-Based Outlier Degrees on Data Sets. ICDE Workshops 2005: 1224
- [c18]Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A Clustering Method Using an Irregular Size Cell Graph. RIDE 2005: 19-26
- 2004
- [c17]Shin'ichi Wakabayashi, Kenji Kikuchi: An Instance-Specific Hardware Algorithm for Finding a Maximum Clique. FPL 2004: 516-525
- 2002
- [j7]Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A Divide-and-Conquer Approach to the Minimum k-Way Cut Problem. Algorithmica 32(2): 262-276 (2002)
- [j6]Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide: A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. Systems and Computers in Japan 33(12): 87-96 (2002)
- 2001
- [j5]Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide: Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. Systems and Computers in Japan 32(1): 29-37 (2001)
- 2000
- [c16]Shin'ichi Wakabayashi, Tetsushi Koide, Nayoshi Toshine, Masataka Yamane, Hajime Ueno: Genetic algorithm accelerator GAA-II. ASP-DAC 2000: 9-10
- [c15]Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi: Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. ASP-DAC 2000: 99-104
1990 – 1999
- 1999
- [j4]Tetsushi Koide, Shin'ichi Wakabayashi: A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. Integration 27(1): 57-76 (1999)
- [c14]Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta: An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. ASP-DAC 1999: 37-40
- [c13]Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide: Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. ASP-DAC 1999: 181-184
- 1998
- [c12]Tetsushi Koide, Shin'ichi Wakabayashi: A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. ASP-DAC 1998: 577-583
- [c11]Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide: Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. PPSN 1998: 1028-1037
- 1997
- [j3]Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida: A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. Integration 24(1): 53-77 (1997)
- [c10]Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru: Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. ASP-DAC 1997: 133-140
- 1996
- [j2]Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A three-layer over-the-cell multi-channel router for a new cell model. Integration 21(3): 171-189 (1996)
- [j1]Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: Pin assignment with global routing for VLSI building block layout. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1575-1583 (1996)
- 1995
- [c9]Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A new system partitioning method under performance and physical constraints for multi-chip modules. ASP-DAC 1995
- [c8]Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru: A new performance driven placement method with the Elmore delay model for row based VLSIs. ASP-DAC 1995
- [c7]Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A three-layer over-cell multi-channel routing method for a new cell model. ASP-DAC 1995
- [c6]Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida: An MCM Routing Algorithm Considering Crosstalk. ISCAS 1995: 211-214
- [c5]Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida: A Verification Algorithm for Logic Circuits with Internal Variables. ISCAS 1995: 1920-1923
- 1994
- [c4]Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A Floorplanning Method with Topological Constraint Manipulation. ISCAS 1994: 165-168
- [c3]Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida: On Three-Way Graph Partitioning. ISCAS 1994: 173-176
- [c2]Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida: A Systolic Graph Partitioning Algorithm for VLSI Design. ISCAS 1994: 225-228
- 1993
- [c1]Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida: Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. ISCAS 1993: 2059-2062
Coauthor Index
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last updated on 2013-05-01 23:02 CEST by the dblp team