Jinn-Shyan Wang

Yi-Mao Hsiao, Yuan-Sun Chu, Jeng-Farn Lee, Jinn-Shyan Wang: A high-throughput and high-capacity IPv6 routing lookup system. Computer Networks 57(3): 782-794 (2013)

Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang: Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. IEEE Trans. VLSI Syst. 21(3): 597-601 (2013)

Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang: A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159

Jian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang: Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS. ISSCC 2013: 426-427

Jinn-Shyan Wang, Pei-Yao Chang, Chi-Chang Lin: Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier. IEICE Transactions 95-C(1): 172-175 (2012)

Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh: An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology. Journal of Circuits, Systems, and Computers 21(8) (2012)

Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Yen-Hsiang Yu: A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS. IEEE Trans. on Circuits and Systems 59-II(12): 908-912 (2012)

Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen, Jinn-Shyan Wang: A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security. IEEE Trans. VLSI Syst. 20(5): 841-854 (2012)

Chingwei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang: Towards Process Variation-Aware Power Gating. IEEE Trans. VLSI Syst. 20(11): 1929-1937 (2012)

Jinn-Shyan Wang, Pei-Yao Chang, Tai-Shin Tang, Jia-Wei Chen, Jiun-In Guo: Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 183-192 (2011)

Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh: Design of High-Performance CMOS Level Converters Considering PVT Variations. IEICE Transactions 94-C(5): 913-916 (2011)

Jia-Wei Chen, Hsiu-Cheng Chang, Jinn-Shyan Wang, Jiun-In Guo: A dynamic quality-adjustable H.264 intra coder. IEEE Trans. Consumer Electronics 57(3): 1203-1211 (2011)

Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng: A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. ASP-DAC 2011: 73-74

Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh: Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays. IEICE Transactions 93-C(10): 1540-1543 (2010)

Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang: A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. J. Solid-State Circuits 45(5): 1036-1047 (2010)

Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang: A 55nm 1GHz one-cycle-locking de-skewing circuit. ISCAS 2010: 1755-1758

Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chi-Lin Liu, Tien-Fu Chen, Jiun-In Guo, Jinn-Shyan Wang: VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism. IEEE Trans. Circuits Syst. Video Techn. 19(11): 1633-1645 (2009)

Hsiu-Cheng Chang, Jia-Wei Chen, Bing-Tsung Wu, Ching-Lung Su, Jinn-Shyan Wang, Jiun-In Guo: A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications. IEEE Trans. Circuits Syst. Video Techn. 19(12): 1739-1754 (2009)

Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang: A dynamic quality-scalable H.264 video encoder chip. ASP-DAC 2009: 125-126

Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang: No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. DAC 2009: 587-592

Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo: A Dynamic Quality-scalable H.264 Video Encoder. ISCAS 2009: 1932

Tzu-Yuan Kuo, Jinn-Shyan Wang: A low-voltage latch-adder based tree multiplier. ISCAS 2008: 804-807

Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo: A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. SiPS 2007: 521-526

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang: A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264. IEEE Trans. Circuits Syst. Video Techn. 16(4): 472-483 (2006)

Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang: An 830mW, 586kbps 1024-bit RSA chip design. DATE Designers' Forum 2006: 24-29

Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang: A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. DATE Designers' Forum 2006: 239-243

Jia-Wei Chen, Chun-Hao Chang, Chien-Chang Lin, Yi-Huan Yang, Jiun-In Guo, Jinn-Shyan Wang: A Condition-based Intra Prediction Algorithm for H.264/AVC. ICME 2006: 1077-1080

Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo: A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. ISCAS 2006

Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu: Design of STR level converters for SoCs using the multi-island dual-VDD design technique. ISCAS 2006

Jinn-Shyan Wang, Yi-Ming Wang, Chun-Yuan Cheng, Yu-Chia Liu: An improved SAR controller for DLL applications. ISCAS 2006

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen: An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. IEEE Trans. Circuits Syst. Video Techn. 15(5): 704-715 (2005)

Yi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang: An all-digital pulsewidth control loop. ISCAS (2) 2005: 1258-1261

Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh: A low-power high-SFDR CMOS direct digital frequency synthesizer. ISCAS (2) 2005: 1670-1673

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang: An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. ISCAS (5) 2005: 4517-4520

Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo: An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. ISLPED 2005: 155-160

Yi-Ming Wang, Jinn-Shyan Wang: A reliable low-power fast skew-compensation circuit. ASP-DAC 2004: 547-548

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh: A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. ICME 2004: 1683-1686

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen: A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. ISCAS (2) 2004: 141-144

Jinn-Shyan Wang, Shang-Jyh Shieh, Ching-Wei Yeh, Yuan-Hsun Yeh: Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs. ISCAS (2) 2004: 401-404

Yi-Ming Wang, Jinn-Shyan Wang: An all-digital 50% duty-cycle corrector. ISCAS (2) 2004: 925-928

Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang: Low-power fixed-width array multipliers. ISLPED 2004: 307-312

Hung-Cheng Wu, Tien-Fu Chen, Hung-Yu Li, Jinn-Shyan Wang: Energy Efficient Caching-on-Cache Architectures for Embedded Systems. J. Inf. Sci. Eng. 19(5): 809-825 (2003)

Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen: Design theory and implementation for low-power segmented bus systems. ACM Trans. Design Autom. Electr. Syst. 8(1): 38-54 (2003)

Yuan-Pao Hsu, Kao-Shing Hwang, Jinn-Shyan Wang: An Associative Architecture of CMAC for Mobile Robot Motion Control. J. Inf. Sci. Eng. 18(2): 145-161 (2002)

Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang: Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 266-280 (2001)

Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang: A high-speed CMOS incrementer/decrementer. ISCAS (4) 2001: 88-91

Sheng-Yeh Lai, Jinn-Shyan Wang: A high-efficiency CMOS charge pump circuit. ISCAS (4) 2001: 406-409

Jinn-Shyan Wang, Po-Hui Yang: Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier. ASP-DAC 2000: 225-228

Yuan-Bao Hsu, Kao-Shing Hwang, Chien-Yuan Pao, Jinn-Shyan Wang: A new CMAC neural network architecture and its ASIC realization. ASP-DAC 2000: 481-484

Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang: Charge sharing fault analysis and testing for CMOS domino logic circuits. Asian Test Symposium 2000: 435-440

Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone: Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. DFT 2000: 329-337

Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang: Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. ICCAD 2000: 387-390

J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen: Segmented bus design for low-power systems. IEEE Trans. VLSI Syst. 7(1): 25-29 (1999)

Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang: Technnology Mapping for Low Power. ASP-DAC 1999: 145-148

Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang: Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs. DAC 1999: 62-67

Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone: Charge Sharing Fault Detection for CMOS Domino Logic Circuits. DFT 1999: 77-85

Ching-Rong Chang, Jinn-Shyan Wang: A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM. ISCAS (1) 1999: 254-257

Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang: A cell selection strategy for low power applications. ISCAS (6) 1999: 416-419

Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng: Low-power embedded SRAM macros with current-mode read/write operations. ISLPED 1998: 282-287

Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu: Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS 1995: 1572-1575