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Li-C. Wang
2010 – today
- 2013
[c111]Wen Chen, Li-C. Wang, Jay Bhadra, Magdy S. Abadir: Simulation knowledge extraction and reuse in constrained random processor verification. DAC 2013: 120- [c110]Li-C. Wang: Data mining in design and test processes: basic principles and promises. ISPD 2013: 41-42
- 2012
- [j23]Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Aarti Gupta: Introduction to special section on verification challenges in the concurrent world. ACM Trans. Design Autom. Electr. Syst. 17(3): 19 (2012)
- [c109]Gen-Hen Liu, Charles H.-P. Wen, Li-C. Wang: D2ENDIST: Dynamic and disjoint ENDIST-based layer-2 routing algorithm for cloud datacenters. GLOBECOM 2012: 1611-1616
- [c108]Wen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, Magdy S. Abadir: Novel test detection to improve simulation efficiency - A commercial experiment. ICCAD 2012: 101-108
- [c107]Vinayak Kamath, Wen Chen, Nik Sumikawa, Li-C. Wang: Functional test content optimization for peak-power validation - An experimental study. ITC 2012: 1-10
- [c106]Nik Sumikawa, Jeff Tikkanen, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir: Screening customer returns with multivariate test analysis. ITC 2012: 1-10
- [c105]Nik Sumikawa, Li-C. Wang, Magdy S. Abadir: An experiment of burn-in time reduction based on parametric test analysis. ITC 2012: 1-10
- 2011
- [c104]Dragoljub Gagi Drmanac, Nik Sumikawa, LeRoy Winemberg, Li-C. Wang, Magdy S. Abadir: Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits. DATE 2011: 794-799
- [c103]Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir: Forward prediction based on wafer sort data - A case study. ITC 2011: 1-10
- [c102]Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir: Understanding customer returns from a test perspective. VTS 2011: 2-7
- [e5]Magdy S. Abadir, Jay Bhadra, Li-C. Wang (Eds.): 12th International Workshop on Microprocessor Test and Verification, MTV 2011, Austin, TX, USA, December 5-7, 2011. IEEE 2011, ISBN 978-1-4577-2101-4
- 2010
- [j22]Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir: Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch. IEEE Design & Test of Computers 27(3): 42-53 (2010)
- [j21]Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Foster: Increasing the Efficiency of Simulation-Based Functional Verification Through Unsupervised Support Vector Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 29(1): 138-148 (2010)
- [c101]
- [c100]Janine Chen, Jing Zeng, Li-C. Wang, Michael Mateja: Correlating system test Fmax with structural test Fmax and process monitoring measurements. ASP-DAC 2010: 419-424
- [c99]Po-Hsien Chang, Li-C. Wang: Automatic assertion extraction via sequential data mining of simulation traces. ASP-DAC 2010: 607-612
- [c98]Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir: Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. DAC 2010: 374-379
- [c97]Po-Hsien Chang, Dragoljub Gagi Drmanac, Li-C. Wang: Online selection of effective functional test programs based on novelty detection. ICCAD 2010: 762-769
- [c96]Hui Li, Makram Mansour, Sury Maturi, Li-C. Wang: A new sampling method for analog behavioral modeling. ISCAS 2010: 2908-2911
- [c95]Dragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang: A non-parametric approach to behavioral device modeling. ISQED 2010: 284-290
- [c94]Jing Zeng, Jing Wang, Chia-Ying Chen, Michael Mateja, Li-C. Wang: On evaluating speed path detection of structural tests. ISQED 2010: 570-576
- [c93]Hui Li, Makram Mansour, Sury Maturi, Li-C. Wang: Analog behavioral modeling flow using statistical learning method. ISQED 2010: 872-878
- [c92]Po-Hsien Chang, Li-C. Wang, Jayanta Bhadra: A kernel-based approach for functional test program generation. ITC 2010: 164-173
- [c91]Janine Chen, Brendon Bolin, Li-C. Wang, Jing Zeng, Dragoljub Gagi Drmanac, Michael Mateja: Mining AC delay measurements for understanding speed-limiting paths. ITC 2010: 553-562
- [c90]Sean H. Wu, Sreejit Chakravarty, Li-C. Wang: Impact of multiple input switching on delay test under process variation. VTS 2010: 87-92
- [c89]Janine Chen, Jing Zeng, Li-C. Wang, Jeff Rearick, Michael Mateja: Selecting the most relevant structural Fmax for system Fmax correlation. VTS 2010: 99-104
- [e4]Magdy S. Abadir, Jay Bhadra, Li-C. Wang (Eds.): 11th International Workshop on Microprocessor Test and Verification, MTV 2010, Austin, TX, USA, December 13-15, 2010. IEEE 2010, ISBN 978-0-7695-4354-3
2000 – 2009
- 2009
- [j20]Nicholas Callegari, Pouria Bastani, Li-C. Wang, Magdy S. Abadir: A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1728-1741 (2009)
- [c88]Nicholas Callegari, Pouria Bastani, Li-C. Wang, Sreejit Chakravarty, Alexander Tetelbaum: Path selection for monitoring unexpected systematic timing effects. ASP-DAC 2009: 781-786
- [c87]Nicholas Callegari, Li-C. Wang, Pouria Bastani: Speedpath analysis based on hypothesis pruning and ranking. DAC 2009: 346-351
- [c86]Dragoljub Gagi Drmanac, Frank Liu, Li-C. Wang: Predicting variability in nanoscale lithography processes. DAC 2009: 545-550
- [c85]
- [c84]Nicholas Callegari, Li-C. Wang, Pouria Bastani: Feature based similarity search with application to speedpath analysis. ITC 2009: 1-10
- [c83]Janine Chen, Li-C. Wang, Po-Hsien Chang, Jing Zeng, S. Yu, Michael Mateja: Data learning techniques and methodology for Fmax prediction. ITC 2009: 1-10
- [c82]Dragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang, Magdy S. Abadir: Minimizing outlier delay test cost in the presence of systematic variability. ITC 2009: 1-10
- 2008
- [j19]Pouria Bastani, Li-C. Wang, Magdy S. Abadir: Linking Statistical Learning to Diagnosis. IEEE Design & Test of Computers 25(3): 232-239 (2008)
- [j18]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang: A Clock-Less Jitter Spectral Analysis Technique. IEEE Trans. on Circuits and Systems 55-I(8): 2263-2272 (2008)
- [c81]Pouria Bastani, Kip Killpack, Li-C. Wang, Eli Chiprout: Speedpath prediction based on learning from a small set of examples. DAC 2008: 217-222
- [c80]Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Foster: Functional test selection based on unsupervised support vector analysis. DAC 2008: 262-267
- [c79]Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir: Statistical diagnosis of unmodeled systematic timing effects. DAC 2008: 355-360
- [c78]Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir: Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained. ITC 2008: 1-10
- [c77]Sean H. Wu, Dragoljub Gagi Drmanac, Li-C. Wang: A Study of Outlier Analysis Techniques for Delay Testing. ITC 2008: 1-10
- 2007
- [j17]Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang: Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. IEEE Design & Test of Computers 24(2): 110-111 (2007)
- [j16]Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray: A Survey of Hybrid Techniques for Functional Verification. IEEE Design & Test of Computers 24(2): 112-122 (2007)
- [c76]Li-C. Wang, Pouria Bastani, Magdy S. Abadir: Design-Silicon Timing Correlation A Data Mining Perspective. DAC 2007: 384-389
- [c75]Onur Guzey, Li-C. Wang: Coverage-directed test generation through automatic constraint extraction. HLDVT 2007: 151-158
- [c74]Charles H.-P. Wen, Li-C. Wang, Jayanta Bhadra: An incremental learning framework for estimating signal controllability in unit-level verification. ICCAD 2007: 250-257
- [c73]Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir: Analyzing the risk of timing modeling based on path delay tests. ITC 2007: 1-10
- [c72]Onur Guzey, Li-C. Wang, Jayanta Bhadra: Enhancing signal controllability in functional test-benches through automatic constraint extraction. ITC 2007: 1-10
- [c71]Sean Hsi Yuan Wu, Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir: Statistical analysis and optimization of parametric delay test. ITC 2007: 1-10
- [e3]Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra (Eds.): Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA. IEEE Computer Society 2007, ISBN 978-0-7695-3241-7
- 2006
- [j15]Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng: Simulation-Based Functional Test Generation for Embedded Processors. IEEE Trans. Computers 55(11): 1335-1343 (2006)
- [c70]Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir: Refined statistical static timing analysis through. DAC 2006: 149-154
- [c69]Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Magdy S. Abadir: Extracting a simplified view of design functionality via vector simulation. HLDVT 2006: 195-202
- [c68]Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Hillel Miller, Magdy S. Abadir: Extracting a Simplified View of Design Functionality Based on Vector Simulation. Haifa Verification Conference 2006: 34-49
- [c67]
- [c66]Charles H.-P. Wen, Onur Guzey, Li-C. Wang: Simulation-based functional test justification using a decision-digram-based Boolean data miner. ICCD 2006
- [c65]Leonard Lee, Li-C. Wang: An Efficient Pruning Method to Guide the Search of Precision Tests in Statistical Timing Space. ITC 2006: 1-10
- [c64]Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir: Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective. ITC 2006: 1-10
- [e2]Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra (Eds.): Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA. IEEE Computer Society 2006, ISBN 978-0-7695-2839-7
- 2005
- [j14]Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin: Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator. ACM Trans. Design Autom. Electr. Syst. 10(4): 627-650 (2005)
- [c63]Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen: An Efficient Sequential SAT Solver With Improved Search Strategies. DATE 2005: 1102-1107
- [c62]Leonard Lee, Sean H. Wu, Charles H.-P. Wen, Li-C. Wang: On Generating Tests to Cover Diverse Worst-Case Timing Corners. DFT 2005: 415-426
- [c61]Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng: Simulation-based functional test generation for embedded processors. HLDVT 2005: 3-10
- [c60]Benjamin N. Lee, Hui Li, Li-C. Wang, Magdy S. Abadir: Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects. ITC 2005: 10
- [c59]Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Wei-Ting Liu, Ji-Jan Chen: Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology. ITC 2005: 10
- [c58]Charles H.-P. Wen, Li-C. Wang: Simulation Data Mining for Functional Test Pattern Justification. MTV 2005: 76-83
- [c57]Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak: On Silicon-Based Speed Path Identification. VTS 2005: 35-41
- [c56]Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen: On A Software-Based Self-Test Methodology and Its Application. VTS 2005: 107-113
- [c55]Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir: Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. VTS 2005: 153-160
- [e1]Magdy S. Abadir, Li-C. Wang (Eds.): Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA. IEEE Computer Society 2005
- 2004
- [j13]Magdy S. Abadir, Li-C. Wang: Guest Editors' Introduction: The Verification and Test of Complex Digital ICs. IEEE Design & Test of Computers 21(2): 80-82 (2004)
- [j12]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang: Safety Property Verification Using Sequential SAT and Bounded Model Checking. IEEE Design & Test of Computers 21(2): 132-143 (2004)
- [j11]T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang: New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. IEEE Design & Test of Computers 21(3): 241-247 (2004)
- [j10]Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna: A Signal Correlation Guided Circuit-SAT Solver. J. UCS 10(12): 1629-1654 (2004)
- [j9]Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang: Multilevel circuit clustering for delay minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1073-1085 (2004)
- [j8]Li-C. Wang, Jing-Jia Liou, Kwang-Ting Cheng: Critical path selection for delay fault testing based upon a statistical timing model. IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1550-1565 (2004)
- [c54]Kai Yang, Kwang-Ting Cheng, Li-C. Wang: TranGen: a SAT-based ATPG for path-oriented transition faults. ASP-DAC 2004: 92-97
- [c53]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang: Jitter spectral extraction for multi-gigahertz signal. ASP-DAC 2004: 298-303
- [c52]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang: Efficient reachability checking using sequential SAT. ASP-DAC 2004: 418-423
- [c51]Tao Feng, Li-C. Wang, Kwang-Ting Cheng: Improved symbolic simulation by functional-space decomposition. ASP-DAC 2004: 634-639
- [c50]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang: An efficient finite-domain constraint solver for circuits. DAC 2004: 212-217
- [c49]Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir: On path-based learning and its applications in delay test and diagnosis. DAC 2004: 492-497
- [c48]Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin: Improved Symoblic Simulation by Dynamic Funtional Space Partitioning. DATE 2004: 42-49
- [c47]Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng: Pattern Selection for Testing of Deep Sub-Micron Timing Defects. DATE 2004: 160
- [c46]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang: Random Jitter Extraction Technique in a Multi-Gigahertz Signal. DATE 2004: 286-291
- [c45]Li-C. Wang: Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation. DATE 2004: 692-695
- [c44]Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Andy Lin: On using a 2-domain partitioned OBDD data structure in verification. HLDVT 2004: 49-54
- [c43]Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu: Static statistical timing analysis for latch-based pipeline designs. ICCAD 2004: 468-472
- [c42]Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng: A path-based methodology for post-silicon timing validation. ICCAD 2004: 713-720
- [c41]Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham: On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. ITC 2004: 31-37
- [c40]Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham: On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. MTV 2004: 103-109
- [c39]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang: A Scalable On-Chip Jitter Extraction Technique. VTS 2004: 267-272
- 2003
- [j7]Li-C. Wang, Tao Feng, Kwang-Ting (Tim) Cheng, Magdy S. Abadir, Manish Pandey: Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems. Design Autom. for Emb. Sys. 8(2-3): 173-188 (2003)
- [j6]Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang: Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs. IEEE Design & Test of Computers 20(5): 6-7 (2003)
- [c38]Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, Magdy S. Abadir: Enhanced symbolic simulation for efficient verification of embedded array systems. ASP-DAC 2003: 302-307
- [c37]Chee-Kian Ong, Kwang-Ting (Tim) Cheng, Li-C. Wang: Delta-sigma modulator based mixed-signal BIST architecture for SoC. ASP-DAC 2003: 669-674
- [c36]Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting Cheng: Experience in critical path selection for deep sub-micron delay test and timing validation. ASP-DAC 2003: 751-756
- [c35]Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna: A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. DAC 2003: 436-441
- [c34]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak: Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. DAC 2003: 668-673
- [c33]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir: Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. DATE 2003: 10328-10335
- [c32]Feng Lu, Li-C. Wang, Kwang-Ting Cheng, Ric C.-Y. Huang: A Circuit SAT Solver With Signal Correlation Guided Learning. DATE 2003: 10892-10897
- [c31]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang: A comparison of BDDs, BMC, and sequential SAT for model checking. HLDVT 2003: 157-162
- [c30]Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang: On Structural vs. Functional Testing for Delay Faults. ISQED 2003: 438-441
- [c29]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak: Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. ITC 2003: 339-348
- [c28]Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir: Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC 2003: 1041-1050
- [c27]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou: Diagnosis of Delay Defects Using Statistical Timing Models. VTS 2003: 339-344
- 2002
- [c26]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams: Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC 2002: 371-374
- [c25]Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng: False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. DAC 2002: 566-569
- [c24]Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer: Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults. DFT 2002: 177-185
- [c23]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng: On theoretical and practical considerations of path selection for delay fault testing. ICCAD 2002: 94-100
- [c22]Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir: Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. ITC 2002: 203-212
- [c21]Li-C. Wang, Magdy S. Abadir, Juhong Zhu: On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults. ITC 2002: 398-406
- [c20]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams: Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC 2002: 407-416
- 2001
- [j5]Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang: Defect-Oriented Testing and Defective-Part-Level Prediction. IEEE Design & Test of Computers 18(1): 31-41 (2001)
- [c19]Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang: Module placement with boundary constraints using the sequence-pair representation. ASP-DAC 2001: 515-520
- [c18]Magdy S. Abadir, Li-C. Wang: Verification and Validation of Complex Digital Systems: An Industrial Perspective. ISQED 2001: 11-12
- [c17]Magdy S. Abadir, Juhong Zhu, Li-C. Wang: Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. VTS 2001: 252-259
- 2000
- [j4]Li-C. Wang, Magdy S. Abadir: On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors. J. Electronic Testing 16(1-2): 121-130 (2000)
- [c16]Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu: Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17-
- [c15]Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer: On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Asian Test Symposium 2000: 151-
- [c14]Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer: Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. ITC 2000: 930-939
1990 – 1999
- 1999
- [j3]Li-C. Wang, Magdy S. Abadir: Experience in Validation of PowerPCTM Microprocessor Embedded Arrays. J. Electronic Testing 15(1-2): 191-205 (1999)
- [c13]Li-C. Wang, Magdy S. Abadir: Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors. ITC 1999: 830-838
- [c12]Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer: Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies. ITC 1999: 1031-1037
- [c11]Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer: REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. VTS 1999: 268-274
- 1998
- [j2]Li-C. Wang, Magdy S. Abadir: Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays. J. Electronic Testing 13(2): 121-135 (1998)
- [j1]Li-C. Wang, Magdy S. Abadir, Jing Zeng: On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. ACM Trans. Design Autom. Electr. Syst. 3(4): 524-532 (1998)
- [c10]Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy: Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. DAC 1998: 534-537
- [c9]Li-C. Wang, Magdy S. Abadir, Jing Zeng: Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. DATE 1998: 273-277
- [c8]Arun Chandra, Li-C. Wang, Magdy S. Abadir: Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors. Great Lakes Symposium on VLSI 1998: 362-367
- [c7]Li-C. Wang, Magdy S. Abadir, Jing Zeng: On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. VTS 1998: 260-265
- 1997
- [c6]Li-C. Wang, Magdy S. Abadir: A New Validation Methodology Combining Test and Formal Verification for PowerPCTM Microprocessor Arrays. ITC 1997: 954-963
- 1996
- [c5]Li-C. Wang, M. Ray Mercer, Thomas W. Williams: A Better ATPG Algorithm and Its Design Principles. ICCD 1996: 248-253
- [c4]Li-C. Wang, M. Ray Mercer, Thomas W. Williams: Using Target Faults To Detect Non-Tartget Defects. ITC 1996: 629-638
- 1995
- [c3]Li-C. Wang, M. Ray Mercer, Thomas W. Williams: On Efficiently and Reliably Achieving Low Defective Part Levels. ITC 1995: 616-625
- [c2]Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams: On the decline of testing efficiency as fault coverage approaches 100%. VTS 1995: 74-83
- 1993
- [c1]Albert G. Greenberg, Boris D. Lubachevsky, Li-C. Wang: Experience in Massively Parallel Discrete Event Simulation. SPAA 1993: 193-202
Coauthor Index
[c111] [j23] [c108] [c106] [c105] [c104] [c103] [c102] [e5] [j22] [c98] [e4] [j20] [c82] [j19] [c79] [c78] [j17] [j16] [c76] [c73] [c71] [e3] [c70] [c69] [c68] [c64] [e2] [c60] [c55] [e1] [j13] [c49] [c41] [c40] [j7] [c38] [c33] [c28] [c22] [c21] [c18] [c17] [j4] [j3] [c13] [j2] [j1] [c10] [c9] [c8] [c7] [c6]
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last updated on 2013-05-28 21:40 CEST by the dblp team