Ting-Chi Wang

Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang: Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. IEEE Trans. VLSI Syst. 21(3): 523-532 (2013)

Bo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang: An efficient hybrid synchronization technique for scalable multi-core instruction set simulations. ASP-DAC 2013: 588-593

Wai-Kei Mak, Yu-Chen Lin, Chris Chu, Ting-Chi Wang: Pad Assignment for Die-Stacking System-in-Package Design. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1711-1722 (2012)

Ming-Chao Tsai, Ting-Chi Wang, Ting Ting Hwang: Through-Silicon Via Planning in 3-D Floorplanning. IEEE Trans. VLSI Syst. 19(8): 1448-1457 (2011)

Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao: Simultaneous redundant via insertion and line end extension for yield optimization. ASP-DAC 2011: 633-638

Tsung-Hsien Lee, Yen-Jung Chang, Ting-Chi Wang: An enhanced global router with consideration of general layer directives. ISPD 2011: 53-60

Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang: Enhanced Double Via Insertion Using Wire Bending. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 171-184 (2010)

Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao: Optimal Double Via Insertion With On-Track Preference. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 318-323 (2010)

Yen-Jung Chang, Yu-Ting Lee, Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang: NTHU-Route 2.0: A Robust Global Router for Modern Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1931-1944 (2010)

De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang: Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. ACM Great Lakes Symposium on VLSI 2010: 423-428

Tsung-Hsien Lee, Ting-Chi Wang: Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing. ICCAD 2010: 312-318

Yen-Jung Chang, Tsung-Hsien Lee, Ting-Chi Wang: GLADE: A modern global router considering layer directives. ICCAD 2010: 319-323

Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang: Pad assignment for die-stacking System-in-Package design. ICCAD 2009: 249-255

Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang: Redundant via insertion with wire bending. ISPD 2009: 123-130

Tsung-Hsien Lee, Ting-Chi Wang: Robust layer assignment for via optimization in multi-layer global routing. ISPD 2009: 159-166

Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao: Fast and Optimal Redundant Via Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2197-2208 (2008)

Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang: A new global router for modern designs. ASP-DAC 2008: 232-237

Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang: An MILP-based wire spreading algorithm for PSM-aware layout modification. ASP-DAC 2008: 364-369

Tien-Yuan Hsu, Ting-Chi Wang: A generalized network flow based algorithm for power-aware FPGA memory mapping. DAC 2008: 30-33

Yen-Jung Chang, Yu-Ting Lee, Ting-Chi Wang: NTHU-Route 2.0: a fast and stable global router. ICCAD 2008: 338-343

Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao: Optimal post-routing redundant via insertion. ISPD 2008: 111-117

Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang: Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. ASP-DAC 2007: 238-243

Pei-Ci Wu, Jhih-Rong Gao, Ting-Chi Wang: A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. ASP-DAC 2007: 262-267

Tien-Ting Fang, Ting-Chi Wang: Fast Buffered Delay Estimation Considering Process Variations. ASP-DAC 2007: 702-707

Kuang-Yao Lee, Ting-Chi Wang: Post-routing redundant via insertion for yield/reliability improvement. ASP-DAC 2006: 303-308

Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao: Post-routing redundant via insertion and line end extension with via density consideration. ICCAD 2006: 633-640

Zhong-Ching Lu, Ting-Chi Wang: Concurrent flip-flop and buffer insertion with adaptive blockage avoidance. ASP-DAC 2005: 19-22

Yun-Ru Wu, Ming-Chao Tsai, Ting-Chi Wang: Maze routing with OPC consideration. ASP-DAC 2005: 198-203

Hao-Yueh Hsieh, Ting-Chi Wang: Simple yet effective algorithms for block and I/O buffer placement in flip-chip design. ISCAS (2) 2005: 1879-1882

Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang: Multilevel circuit clustering for delay minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1073-1085 (2004)

Cliff C. N. Sze, Ting-Chi Wang: Optimal circuit clustering for delay minimization under a more general delay model. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 646-651 (2003)

Chin Ngai Sze, Ting-Chi Wang: Performance-driven multi-level clustering for combinational circuits. ASP-DAC 2003: 729-740

S. Dhamdhere, Ningyu Zhou, Ting-Chi Wang: Module placement with pre-placed modules using the corner block list representation. ISCAS (1) 2002: 349-352

Cliff C. N. Sze, Ting-Chi Wang: Optimal circuit clustering with variable interconnect delay. ISCAS (4) 2002: 707-710

Cliff C. N. Sze, Ting-Chi Wang: Multi-Level Circuit Clustering for Delay Minimization. IWLS 2002: 227-232

Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang: Module placement with boundary constraints using the sequence-pair representation. ASP-DAC 2001: 515-520

Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang: Power minization in LUT-based FPGA technology mapping. ASP-DAC 2001: 635-640

Yi-He Jiang, Jianbang Lai, Ting-Chi Wang: Module placement with pre-placed modules using the B*-tree representation. ISCAS (5) 2001: 347-350

En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang: Slicing floorplan design with boundary-constrained modules. ISPD 2001: 124-129

Hsun-Cheng Lee, Ting-Chi Wang: Feasible two-way circuit partitioning with complex resource constraints. ASP-DAC 2000: 435-440

Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer: On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Asian Test Symposium 2000: 151-

Jan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang: Faster and Better Spectral Algorithms for Multi-Way Partitioning. ASP-DAC 1999: 81-

Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu: Routing for symmetric FPGAs and FPICs. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 20-31 (1997)

Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong: Optimal net assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 265-269 (1995)

T. W. Her, Ting-Chi Wang, Martin D. F. Wong: Performance-driven channel pin assignment algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 849-857 (1995)

Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu: Routing for symmetric FPGAs and FPICs. ICCAD 1993: 486-490

Yao-Ping Chen, Ting-Chi Wang, D. F. Wong: A Graph Partitioning Problem for Multiple-chip Design. ISCAS 1993: 1778-1781

Ting-Chi Wang, Martin D. F. Wong: Optimal floorplan area optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 992-1002 (1992)

Ting-Chi Wang, D. F. Wong: A Graph Theoretic Technique to Speed up Floorplan Area Optimization. DAC 1992: 62-68

Ting-Chi Wang, D. F. Wong: An Optimal Algorithm for Floorplan Area Optimization. DAC 1990: 180-186