| 2009 | ||
|---|---|---|
| c9 | Yang Li, Chun Yuan, Yuzhuo Zhong, Yibo Wang: Non-subsampled Contourlet Transform Based Seismic Signal De-noising. CSIE (6) 2009: 456-459 | |
| 2008 | ||
| c8 | Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto: Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC 2008: 772-775 | |
| c7 | Yibo Wang, Yici Cai, Xianlong Hong: A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. ISVLSI 2008: 221-226 | |
| 2007 | ||
| j1 | Yibo Wang, Yici Cai, Xianlong Hong, Yi Zou: Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration. IEICE Transactions 90-A(5): 1028-1037 (2007) | |
| c6 | ||
| c5 | Jun Li, Dejing Dou, Shiwoong Kim, Han Qin, Yibo Wang: On Knowledge-Based Classification of Abnormal BGP Events. ICISS 2007: 267-271 | |
| 2006 | ||
| c4 | Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang: A novel technique integrating buffer insertion into timing driven placement. ISCAS 2006 | |
| c3 | Yibo Wang, Yici Cai, Xianlong Hong: Performance and power aware buffered tree construction. ISCAS 2006 | |
| 2005 | ||
| c2 | Yici Cai, Yibo Wang, Xianlong Hong: A global interconnect optimization algorithm under accurate delay model using solution space smoothing. ISCAS (1) 2005: 93-96 | |
| c1 | Yibo Wang, Yici Cai, Xianlong Hong: A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. VLSI Design 2005: 91-96 | |
| 1 | Yici Cai | |
| 2 | Sheqin Dong | |
| 3 | Dejing Dou | |
| 4 | Satoshi Goto | |
| 5 | Ou He | |
| 6 | Xianlong Hong | |
| 7 | Shiwoong Kim | |
| 8 | Jun Li 0001 | |
| 9 | Yang Li | |
| 10 | Jiayi Liu | |
| 11 | Lijuan Luo | |
| 12 | Han Qin | |
| 13 | Chun Yuan | |
| 14 | Yuzhuo Zhong | |
| 15 | Qiang Zhou | |
| 16 | Yi Zou |
Colors in the list of coauthors
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