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John Wawrzynek
2010 – today
- 2012
[j16]Ilia A. Lebedev, Christopher W. Fletcher, Shaoyi Cheng, James Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek: Exploring Many-Core Design Templates for FPGAs and ASICs. Int. J. Reconfig. Comp. 2012 (2012)- [j15]Mingjie Lin, Yu Bai, John Wawrzynek: Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience. J. Electrical and Computer Engineering 2012 (2012)
- [c42]Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic: Chisel: constructing hardware in a Scala embedded language. DAC 2012: 1216-1225
- [c41]Shaoyi Cheng, Mingjie Lin, Hao Jun Liu, Simon Scott, John Wawrzynek: Exploiting Memory-Level Parallelism in Reconfigurable Accelerators. FCCM 2012: 157-160
- 2011
- [c40]
- [c39]John Wawrzynek: Should the academic community launch an open-source FPGA device and tools effort?: evening panel. FPGA 2011: 3-4
- [c38]Christopher W. Fletcher, Ilia A. Lebedev, Narges Bani Asadi, Daniel Burke, John Wawrzynek: Bridging the GPGPU-FPGA efficiency gap. FPGA 2011: 119-122
- [c37]Mingjie Lin, Shaoyi Cheng, John Wawrzynek: Using many-core architectural templates for FPGA-based computing (abstract only). FPGA 2011: 281
- [c36]Mingjie Lin, Yu Bai, John Wawrzynek: Discriminatively Fortified Computing with Reconfigurable Digital Fabric. HASE 2011: 112-119
- [e2]John Wawrzynek, Katherine Compton (Eds.): Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011. ACM 2011, ISBN 978-1-4503-0554-9
- 2010
- [j14]Mingjie Lin, John Wawrzynek, Abbas El Gamal: Exploring FPGA Routing Architecture Stochastically. IEEE Trans. on CAD of Integrated Circuits and Systems 29(10): 1509-1522 (2010)
- [j13]Mingjie Lin, John Wawrzynek: Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling. IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1858-1869 (2010)
- [c35]Mingjie Lin, Ilia A. Lebedev, John Wawrzynek: High-throughput bayesian computing machine with reconfigurable hardware. FPGA 2010: 73-82
- [c34]Mingjie Lin, Ilia A. Lebedev, John Wawrzynek: OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices. FPL 2010: 458-463
- [c33]Narges Bani Asadi, Christopher W. Fletcher, Greg Gibeling, John Wawrzynek, Wing H. Wong, Garry P. Nolan: ParaLearn: a massively parallel, scalable system for learning interaction networks on FPGAs. ICS 2010: 83-94
- [c32]Ilia A. Lebedev, Shaoyi Cheng, Austin Doupnik, James Martin, Christopher W. Fletcher, Daniel Burke, Mingjie Lin, John Wawrzynek: MARC: A Many-Core Approach to Reconfigurable Computing. ReConFig 2010: 7-12
- [c31]Mingjie Lin, Shaoyi Cheng, John Wawrzynek: Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations. ReConFig 2010: 103-108
- [e1]Peter Y. K. Cheung, John Wawrzynek (Eds.): Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010. ACM 2010, ISBN 978-1-60558-911-4
2000 – 2009
- 2009
- [j12]Krste Asanovic, Rastislav Bodík, James Demmel, Tony Keaveny, Kurt Keutzer, John Kubiatowicz, Nelson Morgan, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel, Katherine A. Yelick: A view of the parallel computing landscape. Commun. ACM 52(10): 56-67 (2009)
- [c30]Yury Markovsky, Yatish Patel, John Wawrzynek: Using adaptive routing to compensate for performance heterogeneity. NOCS 2009: 12-21
- [c29]Marghoob Mohiyuddin, Mark Murphy, Leonid Oliker, John Shalf, John Wawrzynek, Samuel Williams: A design methodology for domain-optimized power-efficient supercomputing. SC 2009
- 2008
- [j11]Jan M. Rabaey, Daniel Burke, Ken Lutz, John Wawrzynek: Workloads of the Future. IEEE Design & Test of Computers 25(4): 358-365 (2008)
- 2007
- [j10]John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic: RAMP: Research Accelerator for Multiple Processors. IEEE Micro 27(2): 46-57 (2007)
- [c28]
- [c27]Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz: RAMP Blue: A Message-Passing Manycore System in FPGAs. FPL 2007: 54-61
- 2006
- [j9]André DeHon, Randy Huang, John Wawrzynek: Stochastic spatial routing for reconfigurable networks. Microprocessors and Microsystems 30(6): 301-318 (2006)
- [j8]André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek: Stream computations organized for reconfigurable execution. Microprocessors and Microsystems 30(6): 334-354 (2006)
- 2005
- [j7]Chen Chang, John Wawrzynek, Robert W. Brodersen: BEE2: A High-End Reconfigurable Computing System. IEEE Design & Test of Computers 22(2): 114-125 (2005)
- [c26]Chen Chang, John Wawrzynek, Pierre-Yves Droz, Robert W. Brodersen: The Design And Application Of A High-End Reconfigurable Computing System. ERSA 2005: 129-136
- [c25]
- 2004
- [c24]Nicholas Weaver, John R. Hauser, John Wawrzynek: The SFRA: a corner-turn FPGA architecture. FPGA 2004: 3-12
- 2003
- [j6]John Wawrzynek, Keith Diefendorff: Guest Editors' Introduction: Hot Chips 14 - Innovation in the Face of Uncertain Economics. IEEE Micro 23(2): 8-11 (2003)
- [c23]Randy Huang, John Wawrzynek, André DeHon: Stochastic, spatial routing for hypergraphs, trees, and meshes. FPGA 2003: 78-87
- [c22]Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek: Post-placement C-slow retiming for the xilinx virtex FPGA. FPGA 2003: 185-194
- 2002
- [c21]
- [c20]Nicholas Weaver, John Wawrzynek: The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks. FCCM 2002: 303-
- [c19]Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon: Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. FPGA 2002: 196-205
- 2001
- [c18]
- 2000
- [j5]Timothy J. Callahan, John R. Hauser, John Wawrzynek: The Garp Architecture and C Compiler. IEEE Computer 33(4): 62-69 (2000)
- [c17]Nicholas Weaver, John Wawrzynek: A Comparison of the AES Candidates Amenability to FPGA Implementation. AES Candidate Conference 2000: 28-39
- [c16]Timothy J. Callahan, John Wawrzynek: Adapting software pipelining for reconfigurable computing. CASES 2000: 57-64
- [c15]Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon: Stream Computations Organized for Reconfigurable Execution (SCORE). FPL 2000: 605-614
1990 – 1999
- 1999
- [j4]John Lazzaro, John Wawrzynek: JPEG Quality Transcoding Using Neural Networks Trained With a Perceptual Error Measure. Neural Computation 11(1): 267-296 (1999)
- [c14]André DeHon, John Wawrzynek: Reconfigurable Computing: What, Why, and Implications for Design Automation. DAC 1999: 610-615
- [c13]William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon: HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. FPGA 1999: 125-134
- 1998
- [c12]Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek: Object Oriented Circuit-Generators in Java. FCCM 1998: 158-166
- [c11]Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek: Fast Module Mapping and Placement for Datapaths in FPGAs. FPGA 1998: 123-132
- [c10]Timothy J. Callahan, John Wawrzynek: Instruction-Level Parallelism for Reconfigurable Computing. FPL 1998: 248-257
- 1997
- [c9]John R. Hauser, John Wawrzynek: Garp: a MIPS processor with a reconfigurable coprocessor. FCCM 1997: 12-21
- [c8]Timothy J. Callahan, John Wawrzynek: Datapath-oriented FPGA mapping and placement for configurable computing. FCCM 1997: 234-235
- 1996
- [j3]John Wawrzynek, Krste Asanovic, Brian Kingsbury, David Johnson, James Beck, Nelson Morgan: Spert-II: A Vector Microprocessor System. IEEE Computer 29(3): 79-86 (1996)
- [c7]John Lazzaro, John Wawrzynek, Richard Lippmann: A Micropower Analog VLSI HMM State Decoder for Wordspotting. NIPS 1996: 727-733
- 1995
- [c6]John Lazzaro, John Wawrzynek: A multi-sender asynchronous extension to the AER protocol. ARVLSI 1995: 158-171
- [c5]John Wawrzynek, Krste Asanovic, Brian Kingsbury, James Beck, David Johnson, Nelson Morgan: SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training. NIPS 1995: 619-625
- [c4]
- 1993
- [j2]Krste Asanovic, James Beck, Jerry Feldman, Nelson Morgan, John Wawrzynek: Designing A Connectionist Network Supercomputer. Int. J. Neural Syst. 4(4): 317-326 (1993)
- [j1]Krste Asanovic, Nelson Morgan, John Wawrzynek: Using simulations of reduced precision arithmetic to design a neuro-microprocessor. VLSI Signal Processing 6(1): 33-44 (1993)
- 1992
- [c3]John Lazzaro, John Wawrzynek, Misha Mahowald, Massimo Sivilotti, Dave Gillespie: Silicon Auditory Processors as Computer Peripherals. NIPS 1992: 820-827
- 1991
- [c2]David E. Culler, Anurag Sah, Klaus E. Schauser, Thorsten von Eicken, John Wawrzynek: Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine. ASPLOS 1991: 164-175
- [c1]Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya: A Two-Dimensional Topological Compactor With Octagonal Geometry. DAC 1991: 727-731
Coauthor Index
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last updated on 2012-12-02 20:40 CET by the dblp team