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Carl Werner
2010 – today
- 2011
[j1]Shreyas Sen, Farshid Aryanfar, Carl Werner: A Multiband Transceiver System in 45-nm CMOS for Extended Data Rate through Notchy Wireline Channels. IEEE Trans. on Circuits and Systems 58-II(9): 545-549 (2011)- 2010
[c2]Ting Wu, Farshid Aryanfar, Hae-Chang Lee, Jie Shen, T. J. Chin, Carl Werner, Ken Chang: Low-skew clock distribution using zero-phase-clock-buffer DLLs. ISSCC 2010: 176-177
2000 – 2009
- 2004
[c1]Sokratis D. Vamvakos, Carl Werner, Borivoje Nikolic: Phase-locked loop architecture for adaptive jitter optimization. ISCAS (4) 2004: 161-164
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last updated on 2012-12-02 21:32 CET by the dblp team



