- CSB - MetaPress - Google - Bing - Yahoo
 | 2013 | |
|---|---|---|
| c64 |      | Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler: Improving the mapping of reversible circuits to quantum circuits using multiple target lines. ASP-DAC 2013: 145-150 |
| c63 | | Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler: Determining relevant model elements for the verification of UML/OCL specifications. DATE 2013: 1189-1192 |
| c62 | | Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler: Towards a generic verification methodology for system models. DATE 2013: 1193-1196 |
| c61 |  | Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler: Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen. MBMV 2013: 99-103 |
| 2012 | ||
| j10 | | Rolf Drechsler, Irek Ulidowski, Robert Wille: Foreword: Special Issue on Reversible Computation. Multiple-Valued Logic and Soft Computing 18(1): 1-3 (2012) |
| j9 | | Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler: RevKit: A Toolkit for Reversible Circuit Design. Multiple-Valued Logic and Soft Computing 18(1): 55-65 (2012) |
| j8 | | D. Michael Miller, Robert Wille, Rolf Drechsler: Reducing Reversible Circuit Cost by Adding Lines. Multiple-Valued Logic and Soft Computing 19(1-3): 185-201 (2012) |
| j7 | | Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. Multiple-Valued Logic and Soft Computing 19(4): 361-378 (2012) |
| c60 | | Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler: Synthesis of reversible circuits with minimal lines for large functions. ASP-DAC 2012: 85-92 |
| c59 | | Zahra Sasanian, Robert Wille, D. Michael Miller: Realizing reversible circuits using a new class of quantum gates. DAC 2012: 36-41 |
| c58 | | Robert Wille, Rolf Drechsler, Christof Osewold, Alberto García Ortiz: Automatic design of low-power encoders using reversible circuit synthesis. DATE 2012: 1036-1041 |
| c57 | | Robert Wille, Mathias Soeken, Rolf Drechsler: Debugging of inconsistent UML/OCL models. DATE 2012: 1078-1083 |
| c56 | | Mathias Soeken, Robert Wille, Rolf Drechsler: Eliminating invariants in UML/OCL models. DATE 2012: 1142-1145 |
| c55 | | Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler: Coverage-Driven Stimuli Generation. DSD 2012: 525-528 |
| c54 | | Rolf Drechsler, Mathias Soeken, Robert Wille: Formal Specification Level: Towards verification-driven design based on natural language processing. FDL 2012: 53-58 |
| c53 | | Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille: Completeness-Driven Development. ICGT 2012: 38-50 |
| c52 | | Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler: Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines. ISMVL 2012: 69-74 |
| c51 | | Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler: Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits. ISMVL 2012: 173-178 |
| c50 | | Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler: A Synthesis Flow for Sequential Reversible Circuits. ISMVL 2012: 299-304 |
| c49 | | Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler: Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. ISVLSI 2012: 213-218 |
| c48 | | Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler: Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams. RC 2012: 183-196 |
| c47 | | Mathias Soeken, Robert Wille, Shin-ichi Minato, Rolf Drechsler: Using πDDs in the Design of Reversible Circuits. RC 2012: 197-203 |
| c46 | | Mathias Soeken, Robert Wille, Rolf Drechsler: Assisted Behavior Driven Development Using Natural Language Processing. TOOLS (50) 2012: 269-287 |
| c45 | | Rolf Drechsler, Robert Wille: Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology - (Invited Paper). VDAT 2012: 383-392 |
| e1 | | Alexis De Vos, Robert Wille (Eds.): Reversible Computation - Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers. Lecture Notes in Computer Science 7165, Springer 2012, isbn 978-3-642-29516-4 |
| 2011 | ||
| j6 | | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging reversible circuits. Integration 44(1): 51-61 (2011) |
| c44 | | Hongyan Zhang, Robert Wille, Rolf Drechsler: Improved Fault Diagnosis for Reversible Circuits. Asian Test Symposium 2011: 207-212 |
| c43 | | Mathias Soeken, Robert Wille, Rolf Drechsler: Verifying dynamic aspects of UML models. DATE 2011: 1077-1082 |
| c42 | | Robert Wille, Oliver Keszocze, Rolf Drechsler: Determining the minimal number of lines for large reversible circuits. DATE 2011: 1204-1207 |
| c41 | | Rolf Drechsler, Alexander Finder, Robert Wille: Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms. EvoApplications (2) 2011: 151-161 |
| c40 | | Sebastian Offermann, Robert Wille, Rolf Drechsler: Efficient realization of control logic in reversible circuits. FDL 2011: 1-7 |
| c39 | | Rolf Drechsler, Robert Wille: From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits. ISMVL 2011: 78-85 |
| c38 | | Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler: Designing a RISC CPU in Reversible Logic. ISMVL 2011: 170-175 |
| c37 | | D. Michael Miller, Robert Wille, Zahra Sasanian: Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates. ISMVL 2011: 288-293 |
| c36 | | Robert Wille, Hongyan Zhang, Rolf Drechsler: ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization. ISVLSI 2011: 120-125 |
| c35 | | Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler: Designing a RISC CPU in Reversible Logic. MBMV 2011: 249-258 |
| c34 | | Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler: RevKit: An Open Source Toolkit for the Design of Reversible Circuits. RC 2011: 64-76 |
| c33 | | Mathias Soeken, Robert Wille, Rolf Drechsler: Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models. TAP 2011: 152-170 |
| i1 | | Kenichi Morita, Robert Wille: Design of Reversible and Quantum Circuits (Dagstuhl Seminar 11502). Dagstuhl Reports 1(12): 47-61 (2011) |
| 2010 | ||
| b2 | | Robert Wille, Rolf Drechsler: Towards a Design Flow for Reversible Logic. Springer 2010, isbn 978-90-481-9578-7, pp. I-XIII, 1-184 |
| j5 | | Robert Wille, Rolf Drechsler: Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic. Electr. Notes Theor. Comput. Sci. 253(6): 57-70 (2010) |
| j4 | | Robert Wille, Rolf Drechsler: BDD-Based Synthesis of Reversible Logic. Int. J. of Applied Metaheuristic Computing 1(4): 25-41 (2010) |
| j3 | | Robert Wille, Rolf Drechsler: Synthese reversibler Logik (Synthesizing Reversible Logic). it - Information Technology 52(1): 30-38 (2010) |
| c32 | | Robert Wille, Mathias Soeken, Rolf Drechsler: Reducing the number of lines in reversible circuits. DAC 2010: 647-652 |
| c31 | | Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler: Verifying UML/OCL models using Boolean satisfiability. DATE 2010: 1341-1344 |
| c30 | | Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Synthesizing multiplier in reversible logic. DDECS 2010: 335-340 |
| c29 | | Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Window optimization of reversible and quantum circuits. DDECS 2010: 341-345 |
| c28 | | Robert Wille, Sebastian Offermann, Rolf Drechsler: SyReC: A Programming Language for Synthesis of Reversible Circuits. FDL 2010: 184-189 |
| c27 | | Hans-Jörg Kreowski, Sabine Kuske, Robert Wille: Graph Transformation Units Guided by a SAT Solver. ICGT 2010: 27-42 |
| c26 | | Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler: Enhancing debugging of multiple missing control errors in reversible logic. ACM Great Lakes Symposium on VLSI 2010: 465-470 |
| c25 | | Stefan Frehse, Robert Wille, Rolf Drechsler: Efficient Simulation-Based Debugging of Reversible Logic. ISMVL 2010: 156-161 |
| c24 | | D. Michael Miller, Robert Wille, Rolf Drechsler: Reducing Reversible Circuit Cost by Adding Lines. ISMVL 2010: 217-222 |
| c23 | | Robert Wille, Sebastian Offermann, Rolf Drechsler: SyReC: A Programming Language for Synthesis of Reversible Circuits. MBMV 2010: 21-30 |
| c22 | | Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler: Verifying UML/OCL Models Using Boolean Satisfiability. MBMV 2010: 57-66 |
| 2009 | ||
| b1 | | Robert Wille: Towards a design flow for reversible logic. University of Bremen 2009, pp. 1-158 |
| j2 | | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits. Multiple-Valued Logic and Soft Computing 15(4): 283-300 (2009) |
| j1 | | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 703-715 (2009) |
| c21 | | Robert Wille, Rolf Drechsler: BDD-based synthesis of reversible logic for large functions. DAC 2009: 270-275 |
| c20 | | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging of Toffoli networks. DATE 2009: 1284-1289 |
| c19 | | D. Michael Miller, Robert Wille, Gerhard W. Dueck: Synthesizing Reversible Circuits for Irreversible Functions. DSD 2009: 749-756 |
| c18 | | Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler: SMT-based stimuli generation in the SystemC Verification library. FDL 2009: 1-6 |
| c17 | | Robert Wille: Ein Entwurfsablauf für Reversible Schaltkreise. Ausgezeichnete Informatikdissertationen 2009: 291-300 |
| c16 | | Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler: Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI 2009: 173-176 |
| c15 | | André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler: Evaluation of Cardinality Constraints on SMT-Based Debugging. ISMVL 2009: 298-303 |
| c14 | | Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. ISMVL 2009: 324-330 |
| c13 | | Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. MBMV 2009: 67-76 |
| c12 | | Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler: Reversible Logic Synthesis with Output Permutation. VLSI Design 2009: 189-194 |
| 2008 | ||
| c11 | | Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große: Quantified Synthesis of Reversible Logic. DATE 2008: 1015-1020 |
| c10 | | Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler: Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. DSD 2008: 542-549 |
| c9 | | Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler: Contradiction Analysis for Constraint-based Random Simulation. FDL 2008: 130-135 |
| c8 | | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL 2008: 214-219 |
| c7 | | Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler: RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL 2008: 220-225 |
| c6 | | Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler: Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. ISVLSI 2008: 411-416 |
| c5 | | Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler: Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking. MBMV 2008: 169-178 |
| 2007 | ||
| c4 | | Robert Wille, Daniel Große: Fast exact Toffoli network synthesis of reversible logic. ICCAD 2007: 60-64 |
| c3 | | Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler: Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV 2007: 81-90 |
| c2 | | Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler: SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93 |
| 1993 | ||
| c1 | | Kevin Bolding, Sen-Ching Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille: The chaos router chip: design and implementation of an adaptive router. VLSI 1993: 311-320 |
Colors in the list of coauthors
Last update Sun May 19 23:06:52 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page