Steven J. E. Wilton

Kyle Balston, Mehdi Karimibiuki, Alan J. Hu, André Ivanov, Steven J. E. Wilton: Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs. IEEE Trans. Computers 62(2): 242-246 (2013)

Eddie Hung, Steven J. E. Wilton: Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. FPGA 2013: 19-28

Cindy Mark, Scott Y. L. Chin, Lesley Shannon, Steven J. E. Wilton: Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation. ACM Trans. Embedded Comput. Syst. 11(S2): 42 (2012)

Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton: Optimizing Floating Point Units in Hybrid FPGAs. IEEE Trans. VLSI Syst. 20(7): 1295-1303 (2012)

Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang: Formal-Analysis-Based Trace Computation for Post-Silicon Debug. IEEE Trans. VLSI Syst. 20(11): 1997-2010 (2012)

Steven J. E. Wilton, Visvesh Sathe: Advances in 3D design and optimization. CICC 2012: 1

Assem A. M. Bsoul, Steven J. E. Wilton: A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs. FPGA 2012: 245-254

Eddie Hung, Steven J. E. Wilton: Limitations of incremental signal-tracing for FPGA debug. FPL 2012: 49-56

Steven J. E. Wilton, Bradley R. Quinton, Eddie Hung: Rapid RTL-based signal ranking for FPGA prototyping. FPT 2012: 1-7

Assem A. M. Bsoul, Steven J. E. Wilton: An FPGA with power-gated switch blocks. FPT 2012: 87-94

Jeffrey B. Goeders, Steven J. E. Wilton: VersaPower: Power estimation for diverse FPGA architectures. FPT 2012: 229-234

Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton: Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). IEEE Trans. VLSI Syst. 19(12): 2195-2208 (2011)

Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: An Analytical Model Relating FPGA Architecture to Logic Density and Depth. IEEE Trans. VLSI Syst. 19(12): 2229-2242 (2011)

Scott Y. L. Chin, Steven J. E. Wilton: Towards scalable FPGA CAD through architecture. FPGA 2011: 143-152

Joydip Das, Steven J. E. Wilton: An analytical model relating FPGA architecture parameters to routability. FPGA 2011: 181-184

Eddie Hung, Steven J. E. Wilton: Speculative Debug Insertion for FPGAs. FPL 2011: 524-531

Joydip Das, Steven J. E. Wilton: Accelerated FPGA architecture design: Capabilities and limitations of analytical models. FPT 2011: 1-8

Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Resve A. Saleh: Sequence pair based voltage island floorplanning. IGCC 2011: 1-6

Eddie Hung, Steven J. E. Wilton: On evaluating signal selection algorithms for post-silicon debug. ISQED 2011: 290-296

Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton: Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. ReConFig 2011: 41-48

Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward: Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 816-829 (2010)

Steven J. E. Wilton: Towards Analytical Methods for FPGA Architecture Investigation. ARC 2010: 3

Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton: The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). FPGA 2010: 263-272

Assem A. M. Bsoul, Steven J. E. Wilton: An FPGA architecture supporting dynamically controlled power gating. FPT 2010: 1-8

Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aamodt: Accelerating trace computation in post-silicon debug. ISQED 2010: 244-249

Scott Y. L. Chin, Steven J. E. Wilton: Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms. TRETS 1(4) (2009)

Bradley R. Quinton, Steven J. E. Wilton: Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces. IEEE Trans. VLSI Syst. 17(9): 1334-1339 (2009)

Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Floating-Point FPGA: Architecture and Modeling. IEEE Trans. VLSI Syst. 17(12): 1709-1718 (2009)

Xiongfei Meng, Resve Saleh, Steven J. E. Wilton: Charge-borrowing decap: A novel circuit for removal of local supply noise violations. CICC 2009: 25-28

Alastair M. Smith, Steven J. E. Wilton, Joydip Das: Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. FPGA 2009: 181-190

Scott Y. L. Chin, Steven J. E. Wilton: An analytical model relating FPGA architecture and place and route runtime. FPL 2009: 146-153

Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: Modeling post-techmapping and post-clustering FPGA circuit depth. FPL 2009: 205-211

Scott Y. L. Chin, Steven J. E. Wilton: Improving the memory footprint and runtime scalability of FPGA CAD algorithms. FPL 2009: 717-718

Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung: Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT 2009: 54-61

Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong: A detailed delay path model for FPGAs. FPT 2009: 96-103

Sohaib Majzoub, Resve Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward: Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. SoCC 2009: 357-360

Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton: On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays. Int. J. Reconfig. Comp. 2008 (2008)

Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. Int. J. Reconfig. Comp. 2008 (2008)

Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk: A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. TRETS 1(1) (2008)

Julien Lamoureux, Steven J. E. Wilton: On the trade-off between power and flexibility of FPGA clock networks. TRETS 1(3) (2008)

Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton: Practical Asynchronous Interconnect Network Design. IEEE Trans. VLSI Syst. 16(5): 579-588 (2008)

Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. VLSI Syst. 16(11): 1521-1534 (2008)

Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang: BackSpace: Formal Analysis for Post-Silicon Debug. FMCAD 2008: 1-10

Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: An analytical model describing the relationships between logic architecture and FPGA density. FPL 2008: 221-226

Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Rapid estimation of power consumption for hybrid FPGAs. FPL 2008: 227-232

Cindy Mark, Ava Shui, Steven J. E. Wilton: A system-level stochastic circuit generator for FPGA architecture evaluation. FPT 2008: 25-32

Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton: Optimizing coarse-grained units in floating point hybrid FPGA. FPT 2008: 57-64

Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton: BackSpace: Moving Towards Reality. MTV 2008: 49-54

Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton: A synthesizable datapath-oriented embedded FPGA fabric. FPGA 2007: 33-41

Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: an active glitch minimization technique for FPGAs. FPGA 2007: 156-165

Julien Lamoureux, Steven J. E. Wilton: Clock-Aware Placement for FPGAs. FPL 2007: 124-131

Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. FPL 2007: 196-201

Bradley R. Quinton, Steven J. E. Wilton: Embedded Programmable Logic Core Enhancements for System Bus Interfaces. FPL 2007: 202-209

Scott Y. L. Chin, Steven J. E. Wilton: Memory Footprint Reduction for FPGA Routing Algorithms. FPT 2007: 1-8

Andy Yan, Steven J. E. Wilton: Product-Term-Based Synthesizable Embedded Programmable Logic Cores. IEEE Trans. VLSI Syst. 14(5): 474-488 (2006)

Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo: Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. FCCM 2006: 35-44

Julien Lamoureux, Steven J. E. Wilton: FPGA clock network architecture: flexibility vs. area and power. FPGA 2006: 101-108

Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton: Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. FPL 2006: 1-8

Julien Lamoureux, Steven J. E. Wilton: Activity Estimation for Field-Programmable Gate Arrays. FPL 2006: 1-8

Julien Lamoureux, Steven J. E. Wilton: Architecture and CAD for FPGA Clock Networks. FPL 2006: 1-2

Nathalie Chan King Choy, Steven J. E. Wilton: Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs. FPT 2006: 253-256

Steven J. E. Wilton, André DeHon (Eds.): Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006. ACM 2006, isbn 1-59593-292-5

Julien Lamoureux, Steven J. E. Wilton: On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays. J. Low Power Electronics 1(2): 119-132 (2005)

Kara K. W. Poon, Steven J. E. Wilton, Andy Yan: A detailed power model for field-programmable gate arrays. ACM Trans. Design Autom. Electr. Syst. 10(2): 279-302 (2005)

Steven W. Oldridge, Steven J. E. Wilton: A novel FPGA architecture supporting wide, shallow memories. IEEE Trans. VLSI Syst. 13(6): 758-762 (2005)

Peter Hallschmid, Steven J. E. Wilton: Routing architecture optimizations for high-density embedded programmable IP cores. IEEE Trans. VLSI Syst. 13(11): 1320-1324 (2005)

Zion Kwok, Steven J. E. Wilton: Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture. FCCM 2005: 35-44

Gary Chun Tak Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Dynamic Voltage Scaling for Commercial FPGAs. FPT 2005: 173-180

Bradley R. Quinton, Steven J. E. Wilton: Post-Silicon Debug Using Programmable Logic Cores. FPT 2005: 241-248

Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton: Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. ICCD 2005: 267-274

Bradley R. Quinton, Steven J. E. Wilton: Concentrator access networks for programmable logic cores on SoCs. ISCAS (1) 2005: 45-48

Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton: Challenges and opportunities for low power FPGAs in nanometer technologies. ISLPED 2005: 90

Herman Schmit, Steven J. E. Wilton (Eds.): Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005. ACM 2005, isbn 1-59593-029-9

Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong (Eds.): Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005. IEEE 2005, isbn 0-7803-9362-7

Steven J. E. Wilton, Su-Shin Ang, Wayne Luk: The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. FPL 2004: 719-728

Steven J. E. Wilton, Noha Kafafi, Bingfeng Mei, Serge Vernalde: Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays. FPT 2004: 33-40

Tony Wong, Steven J. E. Wilton: Placement and routing for non-rectangular embedded programmable logic cores in SoC design. FPT 2004: 65-72

Steven J. E. Wilton, Christopher W. Jones, Julien Lamoureux: An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array. ISCAS (2) 2004: 885-888

Noha Kafafi, Kimberly Bozman, Steven J. E. Wilton: Architectures and algorithms for synthesizable embedded programmable logic cores. FPGA 2003: 3-11

Steven W. Oldridge, Steven J. E. Wilton: Placement and routing for FPGA architectures supporting wide shallow memories. FPT 2003: 154-161

Andy Yan, Steven J. E. Wilton: Product-term based synthesizable embedded programmable logic cores. FPT 2003: 162-169

Julien Lamoureux, Steven J. E. Wilton: On the Interaction Between Power-Aware FPGA CAD Algorithms. ICCAD 2003: 701-708

Andy Yan, Rebecca Cheng, Steven J. E. Wilton: On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques. FPGA 2002: 147-156

Kara K. W. Poon, Andy Yan, Steven J. E. Wilton: A Flexible Power Model for FPGAs. FPL 2002: 312-321

Steven J. E. Wilton: Implementing logic in FPGA memory arrays: heterogeneous memory architectures. FPT 2002: 142-147

Kara K. W. Poon, Steven J. E. Wilton: Sensitivity of FPGA power evaluation. FPT 2002: 441-442

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Structural analysis and generation of synthetic digital circuits with memory. IEEE Trans. VLSI Syst. 9(1): 223-226 (2001)

Steven J. E. Wilton: A crosstalk-aware timing-driven router for FPGAs. FPGA 2001: 21-28

Peter Hallschmid, Steven J. E. Wilton: Detailed routing architectures for embedded programmable logic IP cores. FPGA 2001: 69-74

Ernie Lin, Steven J. E. Wilton: Macrocell Architectures for Product Term Embedded Memory Arrays. FPL 2001: 48-58

Steven J. E. Wilton: Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 56-68 (2000)

Steven J. E. Wilton: Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. FPGA 2000: 67-74

Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh: FPGA Implementation of a Prototype WDM On-Line Scheduler. FPL 2000: 773-776

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: The memory/logic interface in FPGAs with large embedded memory arrays. IEEE Trans. VLSI Syst. 7(1): 80-91 (1999)

William K. C. Ho, Steven J. E. Wilton: Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. FPL 1999: 111-123

M. Imran Masud, Steven J. E. Wilton: A New Switch Block for Segmented FPGAs. FPL 1999: 274-281

Steven J. E. Wilton: SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. FPGA 1998: 171-178

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. FPGA 1997: 10-16

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Architecture of Centralized Field-Configurable Memory. FPGA 1995: 97-103

Norman P. Jouppi, Steven J. E. Wilton: Tradeoffs in Two-Level On-Chip Caching. ISCA 1994: 34-45

Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton: A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948

Steven J. E. Wilton, Zvonko G. Vranesic: Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. SPDP 1993: 51-55