Roger Woods

Andreas Koch, Roger Woods: Preface - ARC. Microprocessors and Microsystems - Embedded Hardware Design 36(8): 587 (2012)

Qi Zhang, Roger Woods, Alan J. Marshall: An On-Demand Queue Management Architecture for a Programmable Traffic Manager. IEEE Trans. VLSI Syst. 20(10): 1849-1862 (2012)

Stephen McKeown, Roger Woods: Novel Application of Genetic Sequencing Algorithms to Optimization of Hardware Resource Sharing for DSP. ASAP 2012: 169-172

Kenichi Oishi, Hao Huang, Takashi Yoshioka, Sarah H. Ying, David S. Zee, Karl Zilles, Katrin Amunts, Roger Woods, Arthur W. Toga, G. Bruce Pike, Pedro Rosa-Neto, Alan C. Evans, Peter C. M. van Zijl, John C. Mazziotta, Susumu Mori: Superficially Located White Matter Structures Commonly Seen in the Human and the Macaque Brain with Diffusion Tensor Imaging. Brain Connectivity 1(1): 37-47 (2011)

Stephen McKeown, Roger Woods: Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality. IET Computers & Digital Techniques 5(2): 136-144 (2011)

Richard Veitch, Louis-Marie Aubert, Roger Woods, Scott Fischaber: FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition. Int. J. Reconfig. Comp. 2011 (2011)

Shane O'Neill, Roger F. Woods, Alan J. Marshall, Qi Zhang: A Scalable and Programmable Modular Traffic Manager Architecture. TRETS 4(2): 14 (2011)

C. Zheng, Xuezheng Chu, John McAllister, Roger Woods: Real-Valued Fixed-Complexity Sphere Decoder for High Dimensional QAM-MIMO Systems. IEEE Transactions on Signal Processing 59(9): 4493-4499 (2011)

Xuezheng Chu, John McAllister, Roger Woods: A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection. ARC 2011: 133-144

Keanhong Boey, Máire O'Neill, Roger Woods: How Resistant are Sboxes to Power Analysis Attacks? NTMS 2011: 1-6

Andreas Koch, Ram Krishnamurthy, John McAllister, Roger Woods, Tarek A. El-Ghazawi (Eds.): Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings. Lecture Notes in Computer Science 6578, Springer 2011, isbn 978-3-642-19474-0

Brendan McAllister, Alan J. Marshall, Roger F. Woods: A Programmable Architecture for Layered Multimedia Streams in IPv6 Networks. JNW 5(1): 65-74 (2010)

Roger Woods, Jürgen Becker, Peter Athanas, Fearghal Morgan: Guest Editorial ARC 2009. TRETS 4(1): 1 (2010)

Scott Fischaber, Roger Woods, John McAllister: SoC Memory Hierarchy Derivation from Dataflow Graphs. Signal Processing Systems 60(3): 345-361 (2010)

Rongjie Lai, Yonggang Shi, Kevin Scheibel, Scott C. Fears, Roger Woods, Arthur W. Toga, Tony F. Chan: Metric-induced optimal embedding for intrinsic 3D shape analysis. CVPR 2010: 2871-2878

Jianhua Lu, Ji Ming, Roger Woods: Adapting noisy speech models - Extended uncertainty decoding. ICASSP 2010: 4322-4325

Keanhong Boey, Philip Hodgers, Yingxi Lu, Máire O'Neill, Roger Woods: Security of AES Sbox designs to power analysis. ICECS 2010: 1232-1235

Keanhong Boey, Yingxi Lu, Máire O'Neill, Roger Woods: Differential Power Analysis of CAST-128. ISVLSI 2010: 143-148

John McGlone, Roger Woods, Alan J. Marshall, Michaela Blott: Design of a flexible high-speed FPGA-based flow monitor for next generation networks. ICSAMOS 2010: 37-44

Katherine Compton, Roger Woods, Christos-Savvas Bouganis, Pedro C. Diniz: Introduction to the Special Issue ARC'08. TRETS 2(4) (2009)

John McGlone, Alan J. Marshall, Roger Woods: An Attack-Resilent Sampling Mechanism for Integrated IP Flow Monitors. ICDCS Workshops 2009: 233-238

Jianhua Lu, Ji Ming, Roger Woods: Replacing uncertainty decoding with subband re-estimation for large vocabulary speech recognition in noise. INTERSPEECH 2009: 2407-2410

Jürgen Becker, Roger Woods, Peter M. Athanas, Fearghal Morgan (Eds.): Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings. Lecture Notes in Computer Science 5453, Springer 2009, isbn 978-3-642-00640-1

Jürgen Becker, Michael Hübner, Roger Woods, Philip Heng Wai Leong, Robert Esser, Lionel Torres: Current Trends on Reconfigurable Computing. Int. J. Reconfig. Comp. 2008 (2008)

Kenichi Oishi, Karl Zilles, Katrin Amunts, Andreia Faria, Hangyi Jiang, Xin Li, Kazi Akhter, Kegang Hua, Roger Woods, Arthur W. Toga, G. Bruce Pike, Pedro Rosa-Neto, Alan C. Evans, Jiangyang Zhang, Hao Huang, Michael I. Miller, Peter C. M. van Zijl, John C. Mazziotta, Susumu Mori: Human brain white matter atlas: Identification and assignment of common anatomical structures in superficial white matter. NeuroImage 43(3): 447-457 (2008)

Roger F. Woods, John V. McCanny, John G. McWhirter: From Bit Level Systolic Arrays to HDTV Processor Chips. Signal Processing Systems 53(1-2): 35-49 (2008)

Gaye Lightbody, Roger Woods: QR Recursive Least Squares IP Core Example. ECBS 2008: 369-374

Stephen McKeown, Roger Woods, John McAllister: Power efficient DSP datapath configuration methodology for FPGA. FPL 2008: 515-518

Jianhua Lu, Ji Ming, Roger Woods: Combining noise compensation and missing-feature decoding for large vocabulary speech recognition in noise. INTERSPEECH 2008: 1269-1272

John McGlone, Alan J. Marshall, Roger Woods: A real-time flow monitor architecture encompassing on-demand monitoring functions. NOMS 2008: 871-874

Scott Fischaber, John McAllister, Roger Woods: Memory-Centric Hardware Synthesis from Dataflow Models. SAMOS 2008: 197-206

Stephen McKeown, Roger Woods, John McAllister: Power efficient dynamic-range utilisation for DSP on FPGA. SiPS 2008: 233-238

Roger F. Woods, Katherine Compton, Christos-Savvas Bouganis, Pedro C. Diniz (Eds.): Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings. Lecture Notes in Computer Science 4943, Springer 2008, isbn 978-3-540-78609-2

Ed F. Deprettere, Roger Woods, Ingrid Verbauwhede, Erwin A. de Kock: Transforming Signal Processing Applications into Parallel Implementations. EURASIP J. Adv. Sig. Proc. 2007 (2007)

John McAllister, Roger Woods, Scott Fischaber, E. Malins: Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms. Journal of Systems Architecture 53(8): 511-523 (2007)

Erdem Motuk, Roger Woods, Stefan Bilbao, John McAllister: Design Methodology for Real-Time FPGA-Based Sound Synthesis. IEEE Transactions on Signal Processing 55(12): 5833-5845 (2007)

Gaye Lightbody, Roger Woods, Jonathan Francey: Soft IP core implementation of recursive least squares filter using only multplicative and additive operators. FPL 2007: 597-600

Scott Fischaber, Roger Woods, John McAllister: SOC Memory Hierarchy Derivation from Dataflow Graphs. SiPS 2007: 469-474

Ying Yi, Roger Woods: Hierarchical synthesis of complex DSP functions using IRIS. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 806-820 (2006)

John McAllister, Roger Woods, Richard L. Walke, D. Reilly: Multidimensional DSP Core Synthesis for FPGA. VLSI Signal Processing 43(2-3): 207-221 (2006)

John V. McCanny, Roger F. Woods, John G. McWhirter: From Bit Level Systolic Arrays to HDTV Processor Chips. ASAP 2006: 159-162

Scott Fischaber, John McAllister, Roger Woods, E. Malins: Muir Hardware Synthesis for Multimedia Applications. ESTImedia 2006: 101-106

Shane O'Neill, Alan J. Marshall, Roger Woods: Providing Input-Output Throughput Guarantees in a Buffered Crossbar Switch. ISCC 2006: 725-730

Lok-Kee Ting, Roger Woods, C. F. N. Cowan: Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers. IEEE Trans. VLSI Syst. 13(1): 86-95 (2005)

Ying Yi, Roger Woods, Lok-Kee Ting, C. F. N. Cowan: High Speed FPGA-Based Implementations of Delayed-LMS Filters. VLSI Signal Processing 39(1-2): 113-131 (2005)

Erdem Motuk, Roger Woods, Stefan Bilbao: FPGA-Based Hardware for Physical Modelling Sound Synthesis by Finite Difference Schemes. FPT 2005: 103-110

Scott Fischaber, R. Hasson, John McAllister, Roger Woods: FPGA Core Network Implementation and Optimization: A Case Study. FPT 2005: 319-320

Brendan McAllister, Alan J. Marshall, Roger Woods: Programmable Network Functionality for Improved QoS of Interactive Video Traffic. Net-Con 2005: 283-296

Shane O'Neill, Alan J. Marshall, Roger Woods: A Novel Packet Marking Function for Real-Time Interactive MPEG-4 Video Applications in a Differentiated Services Network. NETWORKING 2005: 1031-1042

John McAllister, Roger Woods, D. Reilly, Scott Fischaber, R. Hasson: Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms. SAMOS 2005: 414-423

Lok-Kee Ting, Colin F. N. Cowan, Roger F. Woods: LMS coefficient filtering for Time-varying chirped signals. IEEE Transactions on Signal Processing 52(11): 3160-3169 (2004)

Roger Woods, Russell Tessier: Guest Editorial: Field Programmable Logic. VLSI Signal Processing 36(1): 5-6 (2004)

John McAllister, Roger Woods, Richard L. Walke: Embedded Context Aware Hardware Component Generation for Dataflow System Exploration. SAMOS 2004: 254-263

Gaye Lightbody, Roger Woods, Richard L. Walke: Design of a parameterizable silicon intellectual property core for QR-based RLS filtering. IEEE Trans. VLSI Syst. 11(4): 659-678 (2003)

Richard H. Turner, Roger Woods: Design Flow for Efficient FPGA Reconfiguration. FPL 2003: 972-975

Tim Courtney, Richard H. Turner, Roger Woods: Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes. FCCM 2002: 318-

Richard H. Turner, Roger Woods, Tim Courtney: Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs. FPL 2002: 192-201

Ying Yi, Roger Woods: FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator. FPT 2002: 85-92

Jean-Paul Heron, Roger Woods, Sakir Sezer, Richard H. Turner: Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead. VLSI Signal Processing 28(1-2): 97-113 (2001)

Lok-Kee Ting, Roger Woods, Colin Cowan: Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver. FPL 2001: 367-376

Gordon J. Brebner, Roger Woods (Eds.): Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings. Lecture Notes in Computer Science 2147, Springer 2001, isbn 3-540-42499-7

Gaye Lightbody, Richard L. Walke, Roger Woods, John V. McCanny: Linear QR Architecture for a Single Chip Adaptive Beamformer. VLSI Signal Processing 24(1): 67-81 (2000)

Tim Courtney, Richard H. Turner, Roger Woods: An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing. FCCM 2000: 341-343

Tim Courtney, Richard H. Turner, Roger Woods: Multiplexer Based Reconfiguration for Virtex Multipliers. FPL 2000: 749-758

Jean-Paul Heron, Roger Woods: Accelerating Run-Time Reconfiguration on FCCMs. FCCM 1999: 260-261

Richard H. Turner, Roger Woods, Sakir Sezer, Jean-Paul Heron: A Virtual Hardware Handler for RTR Systems. FCCM 1999: 262-263

Roger Woods, David W. Trainor, Jean-Paul Heron: Applying an XC6200 to Real-Time Image Processing. IEEE Design & Test of Computers 15(1): 30-38 (1998)

Sakir Sezer, Roger Woods, Jean-Paul Heron, Alan J. Marshall: Fast Partial Reconfiguration for FCCMs. FCCM 1998: 318-319

Gareth Keane, Jonathan Spanier, Roger Woods: The impact of data characteristics and hardware topology on hardware selection for low power DSP. ISLPED 1998: 94-96

David W. Trainor, Roger F. Woods, John V. McCanny: Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS". VLSI Signal Processing 16(1): 41-55 (1997)

Roger Woods, Stefan H.-M. Ludwig, Jean-Paul Heron, David W. Trainor, Stephan W. Gehring: FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again). FCCM 1997: 155-164

Colin C. W. Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods: A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation. ASAP 1996: 83-92

David W. Trainor, Roger Woods: Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays. FPL 1996: 116-125

Jean-Paul Heron, Roger Woods: Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA. FPL 1996: 317-326

O. C. McNally, John V. McCanny, Roger F. Woods: Design of a Highly Pipelined 2nd Order IIR Filter Chip. VLSI 1991: 19-28

S. C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny: Bit-Level systolic architectures for high performance IIR filtering. VLSI Signal Processing 1(1): 9-24 (1989)