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Allen C.-H. Wu
2000 – 2009
- 2007
[j19]Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu: Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 564-573 (2007)- 2006
- [j18]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: Decomposition of instruction decoders for low-power designs. ACM Trans. Design Autom. Electr. Syst. 11(4): 880-889 (2006)
- [j17]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: A power-driven multiplication instruction-set design method for ASIPs. IEEE Trans. VLSI Syst. 14(1): 81-85 (2006)
- [c36]Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu: Performance-driven crosstalk elimination at post-compiler level. ISCAS 2006
- 2005
- [c35]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: A power-driven multiplication instruction-set design method for ASIPs. ISCAS (4) 2005: 3311-3314
- [c34]Bing-Fei Wu, Chuan-Tsai Lin, Chao-Jung Chen, Tze-Chiuan Lai, Hsueh-Lung Liao, Allen C.-H. Wu: A fast lane and vehicle detection approach for autonomous vehicles. SIP 2005: 305-310
- 2004
- [c33]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: Decomposition of Instruction Decoder for Low Power Design. DATE 2004: 664-665
- 2003
- [c32]Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. DATE 2003: 11102-11103
- [c31]Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. DATE 2003: 11134-11135
- 2002
- [c30]M.-J. Liao, C.-F. Su, Alex C.-Y. Chang, Allen C.-H. Wu: A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers. ISCAS (1) 2002: 81-84
- [c29]J. C.-Y. Kao, C.-F. Su, Allen C.-H. Wu: High-performance FIR generation based on a timing-driven architecture and component selection method. ISCAS (4) 2002: 759-762
- 2001
- [c28]Peng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu: An RTL design-space exploration method for high-level applications. ASP-DAC 2001: 162-168
- 2000
- [j16]Wen-Jong Fang, Allen C.-H. Wu: Multiway FPGA partitioning by fully exploiting design hierarchy. ACM Trans. Design Autom. Electr. Syst. 5(1): 34-50 (2000)
- [j15]Chi-Hong Hwang, Allen C.-H. Wu: A predictive system shutdown method for energy saving of event-driven computation. ACM Trans. Design Autom. Electr. Syst. 5(2): 226-241 (2000)
- [j14]Allen C.-H. Wu, Nikil D. Dutt: Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). IEEE Trans. VLSI Syst. 8(5): 469-471 (2000)
- [c27]Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud: Embedded tutorial: essential issues for IP reuse. ASP-DAC 2000: 37-42
- [c26]Chien-Chu Kuo, Allen C.-H. Wu: Delay Budgeting for a Timing-Closure-Driven Design Method. ICCAD 2000: 202-207
1990 – 1999
- 1999
- [j13]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 475-483 (1999)
- [j12]Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen: EmGen-a module generator for logic emulation applications. IEEE Trans. VLSI Syst. 7(4): 488-492 (1999)
- [c25]Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu: A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. ASP-DAC 1999: 351-354
- [c24]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. DAC 1999: 262-267
- [c23]Kun-Ming Ho, Allen C.-H. Wu: Module Generation of High Performance FPGA-Based Multipliers. FPGA 1999: 251
- 1998
- [j11]Wen-Jong Fang, Allen C.-H. Wu: Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs. IEEE Design & Test of Computers 15(2): 65-72 (1998)
- [c22]Wen-Jong Fang, Allen C.-H. Wu: Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication. DAC 1998: 283-286
- [c21]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. ISPD 1998: 12-17
- 1997
- [j10]Yuh-Sheng Lee, Allen C.-H. Wu: A performance and routability-driven router for FPGAs considering path delays. IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 179-185 (1997)
- [j9]Wen-Jong Fang, Allen C.-H. Wu: A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1188-1195 (1997)
- [j8]Yann-Rue Lin, Cheng-Tsung Hwang, Allen C.-H. Wu: Scheduling techniques for variable voltage low power designs. ACM Trans. Design Autom. Electr. Syst. 2(2): 81-97 (1997)
- [c20]Chi-Hong Hwang, Allen C.-H. Wu: An entropy measure for power estimation of Boolean functions. ASP-DAC 1997: 101-106
- [c19]Wei-Liang Ing, Cheng-Tsung Hwang, Allen C.-H. Wu: Evaluating cost-performance tradeoffs for system level applications. ASP-DAC 1997: 233-238
- [c18]Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, Tsair-Chin Lin: DP-Gen: a datapath generator for multiple-FPGA applications. ASP-DAC 1997: 563-568
- [c17]Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen: A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications. DAC 1997: 101-106
- [c16]Wen-Jong Fang, Allen C.-H. Wu: Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. DAC 1997: 518-521
- [c15]Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen: Module Generation of Complex Macros for Logic-Emulation Applications. FPGA 1997: 69-75
- [c14]Chi-Hong Hwang, Allen C.-H. Wu: A predictive system shutdown method for energy saving of event-driven computation. ICCAD 1997: 28-32
- [c13]Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin: Preserving HDL synthesis hierarchy for cell placement. ISPD 1997: 169-174
- 1996
- [j7]Tsing-Gen Lee, Wen-Jong Fang, Allen C.-H. Wu: The Design and Inplementation of a Cooperative Design-view Environment for Interactive Partitioning Applications. Softw., Pract. Exper. 26(10): 1141-1160 (1996)
- [c12]Wen-Jong Fang, Allen C.-H. Wu: A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. ICCAD 1996: 638-643
- 1995
- [j6]Allen C.-H. Wu, Youn-Long Lin: High-Level Synthesis -A Tutorial. IEICE Transactions 78-D(3): 209-218 (1995)
- [j5]Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin: TRACER-fpga: a router for RAM-based FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 371-374 (1995)
- [j4]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1076-1084 (1995)
- [c11]Wen-Jong Fang, Allen C.-H. Wu, Tsing-Gen Lee: EMPAR: an interactive synthesis environment for hardware emulations. ASP-DAC 1995
- [c10]Yuh-Sheng Lee, Allen C.-H. Wu: A Performance and Routability Driven Router for FPGAs Considering Path Delays. DAC 1995: 557-561
- 1994
- [j3]Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski: A transformation-based method for loop folding. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 439-450 (1994)
- [c9]Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin: A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC 1994: 277-281
- [c8]Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: State Assignment for Power and Area Minimization. ICCD 1994: 250-254
- 1993
- [c7]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127
- 1992
- [j2]Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu: Layout placement for sliced architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 102-114 (1992)
- [j1]Allen C.-H. Wu, Daniel D. Gajski: Partitioning algorithms for layout synthesis from register-transfer netlists. IEEE Trans. on CAD of Integrated Circuits and Systems 11(4): 453-463 (1992)
- [c6]Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin: An effective methodology for functional pipelining. ICCAD 1992: 230-233
- [c5]Allen C.-H. Wu, Tedd Hadley, Daniel Gajski: An efficient multi-view design model for real-time interactive synthesis. ICCAD 1992: 328-331
- [c4]Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul: Accurate layout area and delay modeling for system level design. ICCAD 1992: 355-361
- 1991
- [c3]Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski: Layout-Area Models for High-Level Synthesis. ICCAD 1991: 34-37
- 1990
- [c2]Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski: A new algorithm for transistor sizing in CMOS circuits. EURO-DAC 1990: 589-593
- [c1]Allen C.-H. Wu, Daniel Gajski: Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. ICCAD 1990: 144-147
Coauthor Index
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last updated on 2013-05-01 23:01 CEST by the dblp team