An-Yeu Wu

Yen-Kuang Chen, An-Yeu Wu, Magdy A. Bayoumi, Farinaz Koushanfar: Editorial: Low-Power, Intelligent, and Secure Solutions for Realization of Internet of Things. IEEE J. Emerg. Sel. Topics Circuits Syst. 3(1): 1-4 (2013)

Jie-Ren Shih, Yongbo Hu, Ming-Chun Hsiao, Ming-Shing Chen, Wen-Chung Shen, Bo-Yin Yang, An-Yeu Wu, Chen-Mou Cheng: Securing M2M With Post-Quantum Public-Key Cryptography. IEEE J. Emerg. Sel. Topics Circuits Syst. 3(1): 106-116 (2013)

Yen-Liang Chen, Cheng-Zhou Zhan, Ting-Jyun Jheng, An-Yeu Wu: Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems. IEEE Trans. VLSI Syst. 21(4): 747-760 (2013)

Sao-Jie Chen, An-Yeu Andy Wu, Jiang Xu: Networks-on-Chip: Architectures, Design Methodologies, and Case Studies. J. Electrical and Computer Engineering 2012 (2012)

Cheng-Zhou Zhan, Yen-Liang Chen, An-Yeu Wu: Iterative Superlinear-Convergence SVD Beamforming Algorithm and VLSI Architecture for MIMO-OFDM Systems. IEEE Transactions on Signal Processing 60(6): 3264-3277 (2012)

Min-An Chao, Xin-Yu Shih, An-Yeu Wu: Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders. Signal Processing Systems 68(2): 183-202 (2012)

Chun-Yuan Chu, An-Yeu Wu: Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder. Signal Processing Systems 68(2): 233-245 (2012)

Kun-Chih Chen, Shu-Yen Lin, Hui-Shun Hung, An-Yeu Wu: Traffic-Balanced Topology-Aware Multiple Routing Adjustment for Throttled 3D NOC Systems. SiPS 2012: 120-124

Yi-Hsuan Lin, Cheng-Zhou Zhan, Chun-Yuan Chu, An-Yeu Andy Wu: A Low-Complexity Grouping FFT-Based Codebook Searching Algorithm in LTE System. SiPS 2012: 161-166

Kuan-Yu Su, Hsien-Kai Hsin, En-Jui Chang, An-Yeu Andy Wu: ACO-Based Deadlock-Aware Fully-Adaptive Routing in Network-on-Chip Systems. SiPS 2012: 209-214

Yu-Hao Chen, Kuan-Yu Ho, Cheng-Zhou Zhan, An-Yeu Andy Wu: Coherent Image Herding of Inhomogeneous Motion Compensation for Synthetic Transmit Aperture in Ultrasound Image. SiPS 2012: 254-257

Kun-Chih Chen, Shu-Yen Lin, Wen-Chung Shen, An-Yeu Wu: A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks. Design Autom. for Emb. Sys. 15(2): 111-132 (2011)

Chun-Yuan Chu, Chih-Hao Chao, Min-An Chao, An-Yeu Wu: Multi-prediction particle filter for efficient parallelized implementation. EURASIP J. Adv. Sig. Proc. 2011: 53 (2011)

Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu: Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding. IEEE Trans. VLSI Syst. 19(2): 305-318 (2011)

David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq Kuen Lee, Yuan-Hua Chu, An-Yeu Wu: Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. Signal Processing Systems 62(3): 373-382 (2011)

Jia-Ming Chen, Chun-Nan Liu, Jen-Kuei Yang, Shau-Yin Tseng, Wei-Kuan Shih, An-Yeu Wu: Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part II: Application Programming. Signal Processing Systems 62(3): 383-402 (2011)

Cheng-Zhou Zhan, Zih-Ling Liu, An-Yeu Wu: Adaptive thresholding incorporating temporal and spatial information with eigen-based clutter filter for color Doppler processing in ultrasonic systems. SiPS 2011: 361-366

Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, Shu-Yen Lin, An-Yeu Wu: Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon. SoCC 2011: 273-277

Chih-Hao Chao, Tsu-Chu Yin, Shu-Yen Lin, An-Yeu Wu: Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems. SoCC 2011: 284-289

Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, An-Yeu Wu: A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm. IEEE Trans. on Circuits and Systems 57-II(6): 430-434 (2010)

Yen-Liang Chen, An-Yeu Wu: Generalized pipelined tomlinson-harashima precoder design methodology with build-in arbitrary speed-up factors. IEEE Transactions on Signal Processing 58(4): 2375-2382 (2010)

Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, An-Yeu Wu: Regional ACO-based routing for load-balancing in NoC systems. NaBIC 2010: 370-376

Chih-Hao Chao, Kai-Yuan Jheng, Hao-Yu Wang, Jia-Cheng Wu, An-Yeu Wu: Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems. NOCS 2010: 223-230

Kai-Yuan Jheng, Yuan-Jyue Chen, An-Yeu Wu: Multilevel LINC System Designs for Power Efficiency Enhancement of Transmitters. J. Sel. Topics Signal Processing 3(3): 523-532 (2009)

Cheng-Hung Lin, Chun-Yu Chen, Tsung-Han Tsai, An-Yeu Wu: Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder. IEEE Trans. on Circuits and Systems 56-I(5): 1005-1016 (2009)

I-Chyn Wey, You-Gang Chen, Changhong Yu, An-Yeu Wu, Jie Chen: Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits. IEEE Trans. on Circuits and Systems 56-I(11): 2411-2424 (2009)

Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu: A 52-mW 8.29mm² 19-mode LDPC decoder chip for mobile WiMAX applications. ASP-DAC 2009: 121-122

Shu-Yen Lin, Chan-Cheng Hsu, An-Yeu Wu: A Scalable Built-in Self-test/Self-diagnosis Architecture for 2D-Mesh based Chip Multiprocessor Systems. ISCAS 2009: 2317-2320

Min-An Chao, Jen-Yang Wen, Xin-Yu Shih, An-Yeu Wu: A Triple-mode LDPC Decoder Design for IEEE 802.11n SYSTEM. ISCAS 2009: 2445-2448

Yu-Hsin Chen, Yi-Ju Chen, Xin-Yu Shih, An-Yeu Wu: A Channel-Adaptive Early Termination strategy for LDPC decoders. SiPS 2009: 226-231

Shu-Yen Lin, Chun-Hsiang Huang, Chih-Hao Chao, Keng-Hsien Huang, An-Yeu Wu: Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks. IEEE Trans. Computers 57(9): 1156-1168 (2008)

Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu: Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel. IEEE Trans. VLSI Syst. 16(10): 1358-1371 (2008)

I-Chyn Wey, You-Gang Chen, An-Yeu Wu: Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits. IEEE Trans. VLSI Syst. 16(12): 1708-1712 (2008)

Yen-Liang Chen, Ming-Feng Hsu, Jyh-Ting Lai, An-Yeu Wu: Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme. Signal Processing Systems 52(1): 59-73 (2008)

Cheng-Zhou Zhan, Xin-Yu Shih, An-Yeu Wu: High-performance scheduling algorithm for partially parallel LDPC decoder. ICASSP 2008: 3177-3180

Huifei Rao, Jie Chen, V. H. Zhao, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu: An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. ISCAS 2008: 608-611

Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu: Low-power traceback MAP decoding for double-binary convolutional turbo decoder. ISCAS 2008: 736-739

Yen-Liang Chen, Cheng-Zhou Zhan, An-Yeu Wu: Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system. ISCAS 2008: 3150-3153

Chih-Hao Chao, Chun-Yuan Chu, An-Yeu Wu: Location-Constrained Particle Filter human positioning and tracking system. SiPS 2008: 73-76

Chun-Yu Chen, Cheng-Hung Lin, An-Yeu Wu: High-throughput dual-mode single/double binary map processor design for wireless wan. SiPS 2008: 83-87

Ting-Jung Lin, Shu-Yen Lin, An-Yeu Wu: Traffic-balanced IP mapping algorithm for 2D-mesh On-Chip-Networks. SiPS 2008: 200-203

Fan-Min Li, An-Yeu Wu: On the New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold. IEEE Transactions on Signal Processing 55(11): 5506-5516 (2007)

Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee: Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. IEEE Trans. VLSI Syst. 15(2): 236-240 (2007)

Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu: Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. ISCAS 2007: 869-872

Chih-Hao Chao, Yen-Lin Kuo, An-Yeu Wu, Weber Chien: A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance. ISCAS 2007: 1113-1116

Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao: Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. ISCAS 2007: 1803-1806

Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, An-Yeu Wu: A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network. NOCS 2007: 317-322

Kai-Yuan Jheng, Yuan-Jyue Chen, An-Yeu Wu: Multilevel Linc System Design for Power Efficiency Enhancement. SiPS 2007: 31-34

Tzu-Hao Yu, Shih-Yu Sun, Chih-Liang Ding, Pai-Chi Li, An-Yeu Wu: Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems. SiPS 2007: 187-192

Chun-Yuan Chu, Jyh-Ting Lai, An-Yeu Wu: Robust Packet Detector based Automatic Gain Control Algorithm for OFDM-based Ultra-WideBand systems. SiPS 2007: 403-406

Chi-Li Yu, Tzu-Hao Yu, An-Yeu Wu: On the Fixed-Point Properties of Mixed-Scaling-Rotation Cordic Algorithm. SiPS 2007: 430-435

Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu: Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency. SiPS 2007: 493-498

Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, Hen-Wai Tsao: DSP engine design for LINC wireless transmitter systems. ISCAS 2006

Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu: A portable all-digital pulsewidth control loop for SOC applications. ISCAS 2006

Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu: A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. ISCAS 2006

Yu-Hung Lee, Tzu-Hao Yu, Kuo-Ken Huang, An-Yeu Wu: Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems. SiPS 2006: 62-65

Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu: A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold. SiPS 2006: 89-94

Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen: A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-Wideband Systems. SiPS 2006: 165-170

Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen: A Low Cost Packet Detector in OFDM-Based Ultra-Wideband Systems. SiPS 2006: 171-176

Ming-Feng Hsu, Yen-Liang Chen, Kai-Yuan Jheng, An-Yeu Wu: A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System. SiPS 2006: 309-312

Tzu-Hao Yu, Chi-Li Yu, Kai-Yuan Jheng, An-Yeu Wu: On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems. SiPS 2006: 422-427

Chih-Hsiu Lin, An-Yeu Wu: Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture. IEEE Transactions on Signal Processing 53(8-2): 3325-3336 (2005)

Tsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu: A memory-reduced log-MAP kernel for turbo decoder. ISCAS (2) 2005: 1032-1035

I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu: A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. ISCAS (2) 2005: 1074-1077

Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu: A scalable DCO design for portable ADPLL designs. ISCAS (6) 2005: 5449-5452

Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu: Digital signal processing engine design for polar transmitter in wireless communication systems. ISCAS (6) 2005: 6026-6029

Meng-Da Yang, An-Yeu Wu, Jyh-Ting Lai: High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. IEEE Trans. VLSI Syst. 12(2): 218-226 (2004)

Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu: A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. ISCAS (5) 2004: 293-296

Hsiu-Ping Lin, Nancy Fang-Yih Chen, Jyh-Ting Lai, An-Yeu Wu: 1000BASE-T Gigabit Ethernet baseband DSP IC design. ISCAS (4) 2004: 401-404

Ching-Hua Wen, Huai-Yi Hsu, Hung Yang Ko, An-Yeu Wu: Least squares approximation-based ROM-free direct digital frequency synthesizer. ISCAS (2) 2004: 701-704

Kai Huang, Fan-Min Li, Pei-Ling Shen, An-Yeu Wu: VLSI design of dual-mode Viterbi/turbo decoder for 3GPP. ISCAS (2) 2004: 773-776

An-Yeu Wu, Ut-Va Koc, Keshab K. Parhi, Sergios Theodoridis: Editorial. EURASIP J. Adv. Sig. Proc. 2003(13): 1265-1267 (2003)

Jen-Chih Kuo, Ching-Hua Wen, Chih-Hsiu Lin, An-Yeu Wu: VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems. EURASIP J. Adv. Sig. Proc. 2003(13): 1306-1316 (2003)

Huai-Yi Hsu, Sheng-Feng Wang, An-Yeu Wu: A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm. VLSI Signal Processing 34(3): 251-259 (2003)

Jen-Chih Kuo, Ching-Hua Wen, An-Yeu Wu: Implementation of a programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based communication systems. ISCAS (2) 2003: 121-124

Tsun-Shan Chan, Jen-Chih Kuo, An-Yeu Wu: A Reduced-Complexity Fast Algorithm for Software Implementation of the IFFT/FFT in DMT Systems. EURASIP J. Adv. Sig. Proc. 2002(9): 961-974 (2002)

Meng-Da Yang, An-Yeu Wu: A new pipelined adaptive DFE architecture with improved convergence rate. ISCAS (4) 2002: 213-216

Cheng-Shing Wu, An-Yeu Wu: A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller. ISCAS (5) 2002: 453-456

Chih-Chi Wang, An-Yeu Wu, Bor-Ming Wang: A cost-effective TEQ algorithm for ADSL systems. ICC 2001: 398-402

Chi-Li Yu, An-Yeu Wu: An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter. ISCAS (4) 2001: 250-253

An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy: System architecture of an adaptive reconfigurable DSP computing engine. IEEE Trans. Circuits Syst. Video Techn. 8(1): 54-73 (1998)

An-Yeu Wu, K. J. Ray Liu: Algorithm-based low-power transform coding architectures: the multirate approach. IEEE Trans. VLSI Syst. 6(4): 707-718 (1998)

An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-Chieh Liu: Parallel programmable video co-processor design. ICIP 1995: 61-64

An-Yeu Wu, K. J. Ray Liu: A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. ISCAS 1994: 155-158

K. J. Ray Liu, An-Yeu Wu: A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation. ISCAS 1993: 1999-2002