Guiming Wu

Guiming Wu, Yong Dou, Junqing Sun, Gregory D. Peterson: A High Performance and Memory Efficient LU Decomposer on FPGAs. IEEE Trans. Computers 61(3): 366-378 (2012)

Guiming Wu, Xianghui Xie, Yong Dou, Junqing Sun, Dong Wu, Yuan Li: Parallelizing sparse LU decomposition on FPGAs. FPT 2012: 352-359

Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni: A Unified Co-Processor Architecture for Matrix Decomposition. J. Comput. Sci. Technol. 25(4): 874-885 (2010)

Guiming Wu, Yong Dou, Gregory D. Peterson: Blocking LU Decomposition for FPGAs. FCCM 2010: 109-112

Guiming Wu, Yong Dou, Miao Wang: High performance and memory efficient implementation of matrix multiplication on FPGAs. FPT 2010: 134-137

Guiming Wu, Yong Dou, Miao Wang: Automatic synthesis of processor arrays with local memories on FPGAs. FPT 2010: 249-252

Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen: FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing. ICS 2010: 325-336

Yong Dou, Guiming Wu, Jinhui Xu, Xingming Zhou: A coarse-grained reconfigurable computing architecture with loop self-pipelining. Science in China Series F: Information Sciences 52(4): 575-587 (2009)

Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang: A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs. FCCM 2009: 183-190

Guiming Wu, Miao Wang, Yong Dou, Fei Xia: Exploiting Fine-Grained Pipeline Parallelism for Wavefront Computations on Multicore Platforms. ICPP Workshops 2009: 402-408

Yong Dou, Jinhui Xu, Guiming Wu: The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining. ARC 2007: 155-166

Miao Wang, Guiming Wu, Zhiying Wang: Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors. ISPA 2007: 946-957

Jinhui Xu, Guiming Wu, Yong Dou, Yazhuo Dong: Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining. Asia-Pacific Computer Systems Architecture Conference 2006: 567-573