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Kaijie Wu
2010 – today
- 2012
[j17]Tongquan Wei, Piyush Mishra, Kaijie Wu, Junlong Zhou: Quasi-static fault-tolerant scheduling schemes for energy-efficient hard real-time systems. Journal of Systems and Software 85(6): 1386-1399 (2012)- [j16]Kun Ma, Han Liang, Kaijie Wu: Homomorphic Property-Based Concurrent Error Detection of RSA: A Countermeasure to Fault Attack. IEEE Trans. Computers 61(7): 1040-1049 (2012)
- 2011
- [j15]Yu Liu, Kaijie Wu, Ramesh Karri: Scan-based attacks on linear feedback shift register based stream ciphers. ACM Trans. Design Autom. Electr. Syst. 16(2): 20 (2011)
- [c21]
- [c20]
- 2010
- [c19]
- [c18]
2000 – 2009
- 2009
- [c17]
- [i2]Yu Liu, Kaijie Wu, Ramesh Karri: Scan-based Attacks on Linear Feedback Shift Register Based Stream Ciphers. IACR Cryptology ePrint Archive 2009: 584 (2009)
- 2008
- [j14]Tongquan Wei, Piyush Mishra, Kaijie Wu, Han Liang: Fixed-Priority Allocation and Scheduling for Energy-Efficient Fault Tolerance in Hard Real-Time Multiprocessor Systems. IEEE Trans. Parallel Distrib. Syst. 19(11): 1511-1526 (2008)
- 2007
- [j13]Han Liang, Piyush Mishra, Kaijie Wu: Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique. IEEE Trans. Computers 56(2): 243-252 (2007)
- [j12]Kyosun Kim, Kaijie Wu, Ramesh Karri: The Robust QCA Adder Designs Using Composable QCA Building Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 176-183 (2007)
- [c16]Richard Stern, Nikhil Joshi, Kaijie Wu, Ramesh Karri: Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations. FDTC 2007: 112-119
- 2006
- [j11]Kyosun Kim, Kaijie Wu, Ramesh Karri: Quantum-Dot Cellular Automata Design Guideline. IEICE Transactions 89-A(6): 1607-1614 (2006)
- [j10]Nikhil Joshi, Jayachandran Sundararajan, Kaijie Wu, Bo Yang, Ramesh Karri: Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks. IEEE Trans. Computers 55(10): 1230-1239 (2006)
- [j9]Kaijie Wu, Ramesh Karri: Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 413-422 (2006)
- [j8]Nikhil Joshi, Kaijie Wu, Jayachandran Sundararajan, Ramesh Karri: Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1163-1169 (2006)
- [j7]Bo Yang, Kaijie Wu, Ramesh Karri: Secure Scan: A Design-for-Test Architecture for Crypto Chips. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2287-2293 (2006)
- [c15]Tongquan Wei, Piyush Mishra, Kaijie Wu, Han Liang: Online task-scheduling for fault-tolerant low-energy real-time systems. ICCAD 2006: 522-527
- 2005
- [c14]Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu: Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. ASP-DAC 2005: 1192-1195
- [c13]Bo Yang, Kaijie Wu, Ramesh Karri: Secure scan: a design-for-test architecture for crypto chips. DAC 2005: 135-140
- [c12]Kyosun Kim, Kaijie Wu, Ramesh Karri: owards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths. DATE 2005: 1214-1219
- 2004
- [j6]Kaijie Wu, Ramesh Karri: Fault secure datapath synthesis using hybrid time and hardware redundancy. IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1476-1485 (2004)
- [c11]Nikhil Joshi, Kaijie Wu, Ramesh Karri: Concurrent Error Detection Schemes for Involution Ciphers. CHES 2004: 400-412
- [c10]Bo Yang, Kaijie Wu, Ramesh Karri: Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. ITC 2004: 339-344
- [c9]Kaijie Wu, Ramesh Karri, Grigori Kuznetsov, Michael Gössel: Low Cost Concurrent Error Detection for the Advanced Encryption Standard. ITC 2004: 1242-1248
- [i1]Bo Yang, Kaijie Wu, Ramesh Karri: Scan Based Side Channel Attack on Data Encryption Standard. IACR Cryptology ePrint Archive 2004: 83 (2004)
- 2003
- [j5]Kaijie Wu, Piyush Mishra, Ramesh Karri: Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher. Microelectronics Journal 34(1): 31-39 (2003)
- [j4]Kaijie Wu, Ramesh Karri: Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths. IEEE Transactions on Reliability 52(4): 501-511 (2003)
- [c8]Kaijie Wu, Ramesh Karri: Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. ITC 2003: 902-911
- 2002
- [j3]Kaijie Wu, Ramesh Karri: Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1077-1087 (2002)
- [j2]Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1509-1517 (2002)
- [j1]Ramesh Karri, Kaijie Wu: Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. IEEE Trans. VLSI Syst. 10(6): 864-875 (2002)
- [c7]Kaijie Wu, Ramesh Karri: Exploiting Idle Cycles for Algorithm Level Re-Computing. DATE 2002: 842-846
- 2001
- [c6]Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers. DAC 2001: 579-585
- [c5]Kaijie Wu, Ramesh Karri: Idle Cycles Based Concurrent Error Detection of RC6 Encryption. DFT 2001: 200-205
- [c4]Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. DFT 2001: 427-435
- [c3]Kaijie Wu, Ramesh Karri: Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. ICCAD 2001: 537-
- [c2]Kaijie Wu, Ramesh Karri: Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. ITC 2001: 221-229
- 2000
- [c1]Ramesh Karri, Kaijie Wu: Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. ITC 2000: 971-978
Coauthor Index
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last updated on 2012-12-02 21:15 CET by the dblp team