Shianling Wu

Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang: Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. 17(4): 48 (2012)

Kelvin Nelson, Jaga Shanmugavadivelu, Jayanth Mekkoth, Venkat Ghanta, Jun Wu, Fei Zhuang, Hao-Jan Chao, Shianling Wu, Jie Rao, Lizhen Yu, Laung-Terng Wang: Physical-design-friendly hierarchical logic built-in self-test - A case study. ISQED 2012: 1-6

Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu: Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 455-463 (2011)

Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone: Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 299-312 (2010)

Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li: CSER: BISER-based concurrent soft-error resilience. VTS 2010: 153-158

Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li: Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Design & Test of Computers 26(1): 26-35 (2009)

Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, FeiFei Zhao, Laung-Terng Wang: Logic BIST Architecture for System-Level Test and Diagnosis. Asian Test Symposium 2009: 21-26

Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu: Analysis of Resistive Bridging Defects in a Synchronizer. Asian Test Symposium 2009: 443-449

Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu: VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. IEEE Design & Test of Computers 25(2): 122-130 (2008)

Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte: On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT 2008: 143-151

Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li: Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. ITC 2008: 1-9

B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu: At-Speed Logic BIST for IP Cores. CoRR abs/0710.4645 (2007)

Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu: A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing. ITC 2006: 1-10

B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu: At-Speed Logic BIST for IP Cores. DATE 2005: 860-861

Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo: At-Speed Logic BIST Architecture for Multi-Clock Designs. ICCD 2005: 475-478

Shianling Wu, Laung-Terng Wang, Jin Woo Cho, Zhigang Jiang, Boryau Sheu: Test compression and logic BIST at your fingertips. ITC 2005: 2

Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang: UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction. ITC 2005: 8

Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai: VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. ITC 2004: 916-925

Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu: Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17-

Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu: A non-enumerative path delay fault simulator for sequential circuits. ITC 1998: 934-943

Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau: Lessons Learned from Practical Applications of BIST/B-S Technology. Asian Test Symposium 1996: 251-257

Sivanarayana Mallela, Shianling Wu: A Sequential Circuit Test Generation System. ITC 1985: 57-61