| 2012 | ||
|---|---|---|
| c7 | Tsung-Yi Wu, Yi-Chieh Chang, Shang-Ti Chen, I.-Tsun Chiang: A Preliminary Study on Using Augmented Virtuality to Improve Training for Intercollegiate Archers. DIGITEL 2012: 212-216 | |
| 2010 | ||
| j5 | Tsung-Yi Wu, Tzi-Wei Kao, How-Rern Lin: Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs. IEICE Transactions 93-A(12): 2581-2589 (2010) | |
| c6 | Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin: Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. ASP-DAC 2010: 444-449 | |
| 2009 | ||
| j4 | How-Rern Lin, Wei-Hao Chiu, Tsung-Yi Wu: A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates. IEICE Transactions 92-C(4): 386-390 (2009) | |
| j3 | Tsung-Yi Wu, Liang-Ying Lu: Low-Leakage and Low-Power Implementation of High-Speed Logic Gates. IEICE Transactions 92-C(4): 401-408 (2009) | |
| 2008 | ||
| c5 | Jiun-Kuan Wu, Tsung-Yi Wu, Liang-Ying Lu, Kuang-Yao Chen: IR Drop Reduction via a Flip-Flop Resynthesis Technique. ISQED 2008: 78-83 | |
| 2007 | ||
| j2 | Tsung-Yi Wu, Jr-Luen Tzeng: A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost. IEICE Transactions 90-A(12): 2718-2726 (2007) | |
| c4 | Tsung-Yi Wu, Jr-Luen Tzeng, Kuang-Yao Chen: A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost. ASP-DAC 2007: 672-677 | |
| 2001 | ||
| c3 | ||
| 1996 | ||
| j1 | Tsung-Yi Wu, Youn-Long Lin: Register minimization beyond sharing among variables. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1583-1587 (1996) | |
| 1995 | ||
| c2 | ||
| 1994 | ||
| c1 | Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin: A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC 1994: 277-281 | |
Colors in the list of coauthors
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