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Wen Ching Wu
2010 – today
- 2011
[j5]Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Kun-Lun Luo, Wen Ching Wu: A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories. IEEE Trans. VLSI Syst. 19(12): 2184-2194 (2011)- 2010
- [j4]Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao: Diagnosis of MRAM Write Disturbance Fault. IEEE Trans. VLSI Syst. 18(12): 1762-1766 (2010)
- [c10]Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu: CAD reference flow for 3D via-last integrated circuits. ASP-DAC 2010: 187-192
2000 – 2009
- 2008
- [j3]Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu: Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2097-2101 (2008)
- 2007
- [c9]Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao: Diagnosis for MRAM write disturbance fault. ITC 2007: 1-9
- 2006
- [c8]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu: A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. ITC 2006: 1-8
- 2005
- [c7]Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu: Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle. Asian Test Symposium 2005: 106-111
- 2004
- [c6]Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu: MRAM Defect Analysis and Fault Modeli. ITC 2004: 124-133
- [c5]Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu: A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. MTDT 2004: 65-69
- 2000
- [j2]Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir: Oscillation Ring Delay Test for High Performance Microprocessors. J. Electronic Testing 16(1-2): 147-155 (2000)
1990 – 1999
- 1998
- [j1]Wen Ching Wu, Chung-Len Lee, Jwu E. Chen: A Two-Phase Fault Simulation Scheme for Sequential Circuits. J. Inf. Sci. Eng. 14(3): 669-686 (1998)
- 1997
- [c4]Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen: Fault diagnosis of odd-even sorting networks. Asian Test Symposium 1997: 288-
- 1995
- [c3]Wen Ching Wu, Chung-Len Lee, Jwu E. Chen: Identification of robust untestable path delay faults. Asian Test Symposium 1995: 229-
- 1994
- [c2]Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin: Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. EDAC-ETC-EUROASIC 1994: 661
- 1991
- [c1]Wen Ching Wu, Chung-Len Lee: A Probabilistic Testability Measure for Delay Faults. DAC 1991: 440-445
Coauthor Index
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last updated on 2012-12-02 22:17 CET by the dblp team