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 | 2012 | |
|---|---|---|
| j1 |      | Wenqing Wu, Xiaochun Zhu, Seung H. Kang, Kendrick Yuen, Rob Gilmore: Probabilistically Programmed STT-MRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(1): 42-51 (2012) |
| c4 | | Xiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu: Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. ICCAD 2012: 88-94 |
| c3 | | Zhenyu Sun, Hai Li, Wenqing Wu: A dual-mode architecture for fast-switching STT-RAM. ISLPED 2012: 45-50 |
| 2011 | ||
| c2 | | Peiyuan Wang, Xiang Chen, Yiran Chen, Hai Helen Li, Seung H. Kang, Xiaochun Zhu, Wenqing Wu: A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis. CICC 2011: 1-4 |
| c1 | | Zhenyu Sun, Xiuyuan Bi, Hai Helen Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu: Multi retention level STT-RAM cache designs with a dynamic refresh scheme. MICRO 2011: 329-338 |
| 1 | Xiuyuan Bi | |
| 2 | Xiang Chen | |
| 3 | Yiran Chen | |
| 4 | Rob Gilmore | |
| 5 | Seung H. Kang | |
| 6 | Hai Li | |
| 7 | Hai Helen Li | |
| 8 | Zhong-Liang Ong | |
| 9 | Zhenyu Sun | |
| 10 | Peiyuan Wang | |
| 11 | Weng-Fai Wong | |
| 12 | Kendrick Yuen | |
| 13 | Xiaochun Zhu |
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