Xiaoxia Wu

Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Sravanti Addepalli, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Saurabh Joshi, Achal Kathuria, Vincent Lai, Deep Masiwal, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Ronald Yin, Liping Peng, Jang Yong Kang, Sharon Huynh, Huijuan Wang, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Takahiko Hara, Hirofumi Inoue, Luca Fasoli, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader: A 130.7mm² 2-layer 32Gb ReRAM memory device in 24nm technology. ISSCC 2013: 210-211

Xiaoxia Wu, Lian-zhu Zhang: Small Randic Index Ordering of Trees with k Pendant Vertices. Ars Comb. 103: 289-304 (2012)

Hualing Zhao, Xiaoxia Wu, Hong Zhang, Hanfeng Chen: Estimating the Proportion of True Null Hypotheses in Nonparametric Exponential Mixture Model with Appication to the Leukemia Gene Expression Data. Communications in Statistics - Simulation and Computation 41(9): 1580-1592 (2012)

Xiaoxia Wu, Wei Zhao, Mark Nakamoto, Chandra Nimmagadda, Durodami Lisk, Sam Gu, Riko Radojcic, Matt Nowak, Yuan Xie: Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs. IEEE Trans. VLSI Syst. 20(1): 186-191 (2012)

Antonella Bogoni, Luca Potì, Alan E. Willner, Paolo Ghelfi, Claudio Porzi, Mirco Scaffardi, Gianluca Meloni, Gianluca Berrettini, Francesco Fresi, Emma Lazzeri, Xiaoxia Wu: Optical logic elementary circuits. IET Circuits, Devices & Systems 5(2): 76-83 (2011)

Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai Helen Li: Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation. IET Computers & Digital Techniques 5(3): 213-220 (2011)

Feng Wang, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan: Variation-Aware Task and Communication Mapping for MPSoC Architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 295-307 (2011)

Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie: Test-access mechanism optimization for core-based three-dimensional SOCs. Microelectronics Journal 41(10): 601-615 (2010)

Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie: Design exploration of hybrid caches with disparate memory technologies. TACO 7(3): 15 (2010)

Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li: Cost-driven 3D integration with interconnect layers. DAC 2010: 150-155

Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie: Scan-chain design and optimization for three-dimensional integrated circuits. JETC 5(2) (2009)

Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yuan Xie: Power and performance of read-write aware Hybrid Caches with non-volatile memories. DATE 2009: 737-742

Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie: Hybrid cache architecture with disparate memory technologies. ISCA 2009: 34-45

Guangyu Sun, Xiaoxia Wu, Yuan Xie: Exploration of 3D stacked L2 cache design for high performance and efficient thermal control. ISLPED 2009: 295-298

Feng Wang, Xiaoxia Wu, Yuan Xie: Variability-driven module selection with joint design time optimization and post-silicon tuning. ASP-DAC 2008: 2-9

Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Helen Li, Yiran Chen: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. DAC 2008: 554-559

Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie: Comparative analysis of NBTI effects on low power and high performance flip-flops. ICCD 2008: 200-205

Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie: Test-access mechanism optimization for core-based three-dimensional SOCs. ICCD 2008: 212-218

Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie: Test-Access Solutions for Three-Dimensional SOCs. ITC 2008: 1

Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: On-chip bus thermal analysis and optimisation. IET Computers & Digital Techniques 1(5): 590-599 (2007)

Feng Wang, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan: Variation-aware task allocation and scheduling for MPSoC. ICCAD 2007: 598-603

Xiaoxia Wu, Paul Falkenstern, Yuan Xie: Scan chain design for three-dimensional integrated circuits (3D ICs). ICCD 2007: 208-214

Wei-Lun Hung, Xiaoxia Wu, Yuan Xie: Guaranteeing performance yield in high-level synthesis. ICCAD 2006: 303-309

Xiaoxia Wu, Feng Wang, Yuan Xie: Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design. SoCC 2006: 91-92