| 2013 | ||
|---|---|---|
| c48 | Cheng Wang, Youfeng Wu: TSO_ATOMICITY: efficient hardware primitive for TSO-preserving region optimizations. ASPLOS 2013: 509-520 | |
| c47 | Cheng Wang, Youfeng Wu, Marcelo Cintra: Acceldroid: Co-designed acceleration of Android bytecode. CGO 2013: 1-10 | |
| 2012 | ||
| j5 | Cheng Wang, Youfeng Wu: From Locks to Correct and Efficient Transactional Memory. Journal of Circuits, Systems, and Computers 21(2) (2012) | |
| c46 | Liang Han, Xiaowei Jiang, Wei Liu, Youfeng Wu, James Tuck: HiRe: using hint & release to improve synchronization of speculative threads. ICS 2012: 143-152 | |
| c45 | Cheng Wang, Youfeng Wu, Hongbo Rong, Hyunchul Park: SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations. MICRO 2012: 425-436 | |
| 2011 | ||
| c44 | Cheng Wang, Youfeng Wu: Modeling and Performance Evaluation of TSO-Preserving Binary Optimization. PACT 2011: 383-392 | |
| c43 | Edson Borin, Youfeng Wu, Mauricio Breternitz Jr., Cheng Wang: LAR-CC: Large atomic regions with conditional commits. CGO 2011: 54-63 | |
| c42 | Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang: A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing. CGO 2011: 236-245 | |
| c41 | Gilles Pokam, Cristiano Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin Emile Gottschlich, Jungwoo Ha, Youfeng Wu: CoreRacer: a practical memory race recorder for multicore x86 TSO processors. MICRO 2011: 216-225 | |
| c40 | Edson Borin, Guido Araujo, Mauricio Breternitz Jr., Youfeng Wu: Structure-Constrained Microcode Compression. SBAC-PAD 2011: 104-111 | |
| 2010 | ||
| c39 | Edson Borin, Youfeng Wu, Cheng Wang, Wei Liu, Mauricio Breternitz Jr., Shiliang Hu, Esfir Natanzon, Shai Rotem, Roni Rosner: TAO: two-level atomicity for dynamic binary optimizations. CGO 2010: 12-21 | |
| c38 | João Paulo Porto, Guido Araujo, Edson Borin, Youfeng Wu: Trace Execution Automata in Dynamic Binary Translation. ISCA Workshops 2010: 99-116 | |
| 2009 | ||
| c37 | Cheng Wang, Youfeng Wu, Edson Borin, Shiliang Hu, Wei Liu, Dave Sager, Tin-fook Ngai, Jesse Fang: Dynamic parallelization of single-threaded binary programs using speculative slicing. ICS 2009: 158-168 | |
| c36 | ||
| 2008 | ||
| c35 | Cheng Wang, Victor Ying, Youfeng Wu: Supporting Legacy Binary Code in a Software Transaction Compiler with Dynamic Binary Translation and Optimization. CC 2008: 291-306 | |
| c34 | Mauricio Breternitz Jr., Gabriel H. Loh, Bryan Black, Jeff Rupley, Peter G. Sassone, Wesley Attrot, Youfeng Wu: A Segmented Bloom Filter Algorithm for Efficient Predictors. SBAC-PAD 2008: 123-130 | |
| 2007 | ||
| c33 | Cheng Wang, Shiliang Hu, Ho-Seop Kim, Sreekumar R. Nair, Mauricio Breternitz Jr., Zhiwei Ying, Youfeng Wu: StarDBT: An Efficient Multi-platform Dynamic Binary Translation System. Asia-Pacific Computer Systems Architecture Conference 2007: 4-15 | |
| c32 | Cheng Wang, Wei-Yu Chen, Youfeng Wu, Bratin Saha, Ali-Reza Adl-Tabatabai: Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language. CGO 2007: 34-48 | |
| c31 | Cheng Wang, Ho-Seop Kim, Youfeng Wu, Victor Ying: Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection. CGO 2007: 244-258 | |
| c30 | Youfeng Wu, Mauricio Breternitz Jr., Victor Ying: Impacts of Multiprocessor Configurations on Workloads in Bioinformatics. SBAC-PAD 2007: 105-113 | |
| 2006 | ||
| j4 | Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks: Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance. IEEE Micro 26(1): 119-129 (2006) | |
| c29 | Bolei Guo, Youfeng Wu, Cheng Wang, Matthew J. Bridges, Guilherme Ottoni, Neil Vachharajani, Jonathan Chang, David I. August: Selective Runtime Memory Disambiguation in a Dynamic Binary Translator. CC 2006: 65-79 | |
| c28 | ||
| c27 | Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo: Software-Based Transparent and Comprehensive Control-Flow Error Detection. CGO 2006: 333-345 | |
| c26 | Edson Borin, Mauricio Breternitz Jr., Youfeng Wu, Guido Araujo: Clustering-Based Microcode Compression. ICCD 2006 | |
| c25 | Feng Qin, Cheng Wang, Zhenmin Li, Ho-Seop Kim, Yuanyuan Zhou, Youfeng Wu: LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks. MICRO 2006: 135-148 | |
| c24 | Chengliang Zhang, Chen Ding, Mitsunori Ogihara, Yutao Zhong, Youfeng Wu: A hierarchical model of data locality. POPL 2006: 16-29 | |
| 2005 | ||
| j3 | Youfeng Wu, Yong-Fong Lee: Hardware-Software Collaborative Techniques for Runtime Profiling and Phase Transition Detection. J. Comput. Sci. Technol. 20(5): 665-675 (2005) | |
| j2 | Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo: Dynamic binary control-flow errors detection. SIGARCH Computer Architecture News 33(5): 15-20 (2005) | |
| c23 | Youfeng Wu, Mauricio Breternitz Jr., Herbert H. J. Hum, Ramesh V. Peri, Jay Pickett: Enhanced code density of embedded CISC processors with echo technology. CODES+ISSS 2005: 160-165 | |
| c22 | Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks: A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. MICRO 2005: 271-282 | |
| 2004 | ||
| c21 | Youfeng Wu, Mauricio Breternitz Jr., Tevi Devor: Continuous Trip Count Profiling for Loop Optimizations in Two-Phase Dynamic Binary Translato. Interaction between Compilers and Computer Architectures 2004: 3-12 | |
| c20 | Youfeng Wu, Yong-Fong Lee: Exploiting Free Execution Slots on EPIC Processors for Efficient and Accurate Runtime Profiling. Asia-Pacific Computer Systems Architecture Conference 2004: 226-240 | |
| c19 | Youfeng Wu, Mauricio Breternitz Jr., Justin Quek, Orna Etzion, Jesse Fang: The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators. CGO 2004: 227-238 | |
| 2003 | ||
| c18 | Li-Ling Chen, Youfeng Wu: Aggressive Compiler Optimization and Parallelization with Thread-Level Speculation. ICPP 2003: 607-614 | |
| c17 | Youfeng Wu, Li-Ling Chen, Roy Ju, Jesse Fang: Performance potentials of compiler-directed data speculation. ISPASS 2003: 22-31 | |
| 2002 | ||
| c16 | Youfeng Wu: Accuracy of Profile Maintenance in Optimizing Compilers. Interaction between Compilers and Computer Architectures 2002: 27-38 | |
| c15 | Youfeng Wu, Mauricio J. Serrano, Rakesh Krishnaiyer, Wei Li, Jesse Fang: Value-Profile Guided Stride Prefetching for Irregular Code. CC 2002: 307-324 | |
| c14 | Youfeng Wu, Ryan Rakvic, Li-Ling Chen, Chyi-Chang Miao, George Chrysos, Jesse Fang: Compiler managed micro-cache bypassing for high performance EPIC processors. MICRO 2002: 134-145 | |
| c13 | Youfeng Wu: Efficient Discovery of Regular Stride Patterns in Irregular Programs. PLDI 2002: 210-221 | |
| 2001 | ||
| c12 | Youfeng Wu, Utpal Banerjee, Yong-Fong Lee: Calculation of Load Invalidation Rates for Data Speculation. ISCA PDCS 2001: 75-82 | |
| c11 | Youfeng Wu, Dong-yuan Chen, Jesse Fang: Better exploration of region-level value locality with integrated computation reuse and value prediction. ISCA 2001: 98-108 | |
| 2000 | ||
| c10 | Hsien-Hsin Lee, Youfeng Wu, Gary Tyson: Quantifying instruction-level parallelism limits on an EPIC architecture. ISPASS 2000: 21-27 | |
| 1999 | ||
| c9 | Youfeng Wu, Yong-Fong Lee: Comprehensive Redundant Load Elimination for the IA-64 Architecture. LCPC 1999: 53-69 | |
| 1996 | ||
| c8 | Pohua P. Chang, Dong-yuan Chen, Yong-Fong Lee, Youfeng Wu, Utpal Banerjee: Bidirectional Scheduling: A New Global Code Scheduling Approach. LCPC 1996: 222-230 | |
| 1995 | ||
| j1 | Youfeng Wu: Strength Reduction of Multiplications by Integer Constants. SIGPLAN Notices 30(2): 42-48 (1995) | |
| 1994 | ||
| c7 | ||
| c6 | Bogong Su, Stanley Habib, Wei Zhao, Jian Wang, Youfeng Wu: A study of pointer aliasing for software pipelining using run-time disambiguation. MICRO 1994: 112-117 | |
| 1992 | ||
| c5 | Youfeng Wu: Ordering functions for improving memory reference locality in a shared memory multiprocessor system. MICRO 1992: 218-221 | |
| 1990 | ||
| c4 | ||
| c3 | Youfeng Wu, Ted G. Lewis: Parallel Algorithms for Decomposable Linear Programs. ICPP (3) 1990: 27-34 | |
| c2 | ||
| 1989 | ||
| c1 | ||
Colors in the list of coauthors
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