Yuan Xie

Pennsylvania State University

other persons with the same name:

• Yuan Xie 0002 - Shanghai Jiao Tong University
• Yuan Xie 0003 - Center for Computational Regulatory Genomics, California Institute of Technology

	2013
j47		Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, Tingting Huang: Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. Integration 46(1): 1-9 (2013)
j46		Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan: A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. JETC 9(1): 5 (2013)
j45		Yuan Xie, Gabriel H. Loh: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 32(4): 485-486 (2013)
c153		Jue Wang, Xiangyu Dong, Yuan Xie: OAP: an obstruction-aware cache management policy for STT-RAM last-level caches. DATE 2013: 847-852
c152		Yuan Xie: Future memory and interconnect technologies. DATE 2013: 964-969
c151		Qiaosha Zou, Tao Zhang, Eren Kursun, Yuan Xie: Thermomechanical stress-aware management for 3D IC designs. DATE 2013: 1255-1258
	2012
j44		Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang: ESL Design Methodology. J. Electrical and Computer Engineering 2012 (2012)
j43		Yibo Chen, Yu Wang, Yuan Xie, Andrés Takach: Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing. J. Electrical and Computer Engineering 2012 (2012)
j42		Yuan Xie, Yanyun Qu, Cuihua Li, Wensheng Zhang: Online multiple instance gradient feature selection for robust visual tracking. Pattern Recognition Letters 33(9): 1075-1082 (2012)
j41		Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi: NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE Trans. on CAD of Integrated Circuits and Systems 31(7): 994-1007 (2012)
j40		Shengqi Yang, Pallav Gupta, Marilyn Wolf, Dimitrios N. Serpanos, Vijaykrishnan Narayanan, Yuan Xie: Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling. ACM Trans. Embedded Comput. Syst. 11(3): 62 (2012)
j39		Guangyu Sun, Huazhong Yang, Yuan Xie: Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs. ACM Trans. Design Autom. Electr. Syst. 17(2): 13 (2012)
j38		Xiaoxia Wu, Wei Zhao, Mark Nakamoto, Chandra Nimmagadda, Durodami Lisk, Sam Gu, Riko Radojcic, Matt Nowak, Yuan Xie: Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs. IEEE Trans. VLSI Syst. 20(1): 186-191 (2012)
c150		Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie: Thermal-aware power network design for IR drop reduction in 3D ICs. ASP-DAC 2012: 47-52
c149		Dimin Niu, Yang Xiao, Yuan Xie: Low power memristor-based ReRAM design with Error Correcting Code. ASP-DAC 2012: 79-84
c148		Jing Xie, Yu Wang, Yuan Xie: Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs. ASP-DAC 2012: 738-743
c147		Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar Iyer, Chita R. Das: Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. DAC 2012: 243-252
c146		Jue Wang, Xiangyu Dong, Yuan Xie: Point and discard: a hard-error-tolerant architecture for non-volatile last level caches. DAC 2012: 253-258
c145		Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie: PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method. DAC 2012: 1191-1196
c144		Yibo Chen, Guangyu Sun, Qiaosha Zou, Yuan Xie: 3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs. DATE 2012: 1185-1190
c143		Guangyu Sun, Cong Xu, Yuan Xie: Modeling and design exploration of FBDRAM as on-chip memory. DATE 2012: 1507-1512
c142		Jing Xie, Vijaykrishnan Narayanan, Yuan Xie: Mitigating electromigration of power supply networks using bidirectional current stress. ACM Great Lakes Symposium on VLSI 2012: 299-302
c141		Jishen Zhao, Yuan Xie: Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration. ICCAD 2012: 81-87
c140		Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie: Design trade-offs for high density cross-point resistive memory. ISLPED 2012: 209-214
c139		Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie: Energy-efficient GPU design with reconfigurable in-package graphics memory. ISLPED 2012: 403-408
c138		Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang: Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits. ISVLSI 2012: 183-188
c137		Matthew Poremba, Yuan Xie: NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories. ISVLSI 2012: 392-397
c136		Sheng Li, Doe Hyun Yoon, Ke Chen, Jishen Zhao, Jung Ho Ahn, Jay B. Brockman, Yuan Xie, Norman P. Jouppi: MAGE: adaptive granularity and ECC for resilient and power efficient memory systems. SC 2012: 33
c135		Jin Liu, Juan Li, Yuan Xie, Jeff Lei, Qiping Hu: An Embedded Co-AdaBoost and Its Application in Classification of Software Document Relation. SKG 2012: 173-180
	2011
j37		Yuan Xie: Modeling, Architecture, and Applications for Emerging Memory Technologies. IEEE Design & Test of Computers 28(1): 44-51 (2011)
j36		Vinay Saripalli, Guangyu Sun, Asit K. Mishra, Yuan Xie, Suman Datta, Vijaykrishnan Narayanan: Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 109-119 (2011)
j35		Guangyu Sun, Yibo Chen, Xiangyu Dong, Jin Ouyang, Yuan Xie: Three-dimensional Integrated Circuits: Design, EDA, and Architecture. Foundations and Trends in Electronic Design Automation 5(1-2): 1-151 (2011)
j34		Yuan Xie, Pol Marchal: Editorial- three-dimensional integrated circuits design. IET Computers & Digital Techniques 5(3): 159 (2011)
j33		Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai Helen Li: Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation. IET Computers & Digital Techniques 5(3): 213-220 (2011)
j32		Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi: Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. TACO 8(2): 6 (2011)
j31		Feng Wang, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan: Variation-Aware Task and Communication Mapping for MPSoC Architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 295-307 (2011)
j30		Feng Wang, Yuan Xie: Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model. IEEE Trans. Dependable Sec. Comput. 8(1): 137-146 (2011)
j29		Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie: Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation. IEEE Trans. Dependable Sec. Comput. 8(5): 756-769 (2011)
j28		Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang: Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques. IEEE Trans. VLSI Syst. 19(4): 615-628 (2011)
c134		Xiangyu Dong, Yuan Xie: AdaMS: Adaptive MLC/SLC phase-change memory design for file storage. ASP-DAC 2011: 31-36
c133		Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang: On-chip hybrid power supply system for wireless sensor nodes. ASP-DAC 2011: 43-48
c132		Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie: A frequent-value based PRAM memory architecture. ASP-DAC 2011: 211-216
c131		Jin Ouyang, Yuan Xie: Enabling quality-of-service in nanophotonic network-on-chip. ASP-DAC 2011: 351-356
c130		Qiaosha Zou, Yibo Chen, Yuan Xie, Alan Su: System-level design space exploration for three-dimensional (3D) SoCs. CODES+ISSS 2011: 385-388
c129		Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan: Automated mapping for reconfigurable single-electron transistor arrays. DAC 2011: 878-883
c128		Jishen Zhao, Xiangyu Dong, Yuan Xie: An energy-efficient 3D CMP design with fine-grained voltage scaling. DATE 2011: 539-542
c127		Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie: Design implications of memristor-based RRAM cross-point structures. DATE 2011: 734-739
c126		Vijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta: Enabling architectural innovations using non-volatile memory. ACM Great Lakes Symposium on VLSI 2011: 439-444
c125		Shekhar Srikantaiah, Emre Kultursay, Tao Zhang, Mahmut T. Kandemir, Mary Jane Irwin, Yuan Xie: MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy. HPCA 2011: 231-242
c124		Jishen Zhao, Cong Xu, Yuan Xie: Bandwidth-aware reconfigurable cache design with hybrid memory technologies. ICCAD 2011: 48-55
c123		Cong Xu, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Matt Nowak, Yuan Xie: Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. ICCAD 2011: 463-470
c122		Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie: Energy-efficient multi-level cell phase-change memory system with data encoding. ICCD 2011: 175-182
c121		Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie: Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory. ICCD 2011: 366-372
c120		Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu: F2BFLY: an on-chip free-space optical network with wavelength-switching. ICS 2011: 348-358
c119		Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das: Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA 2011: 69-80
c118		Guangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen: Moguls: a model to explore the memory hierarchy for bandwidth improvements. ISCA 2011: 377-388
c117		Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie: Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs. ISLPED 2011: 397-402
c116		Han-Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan: Impact of Circuit Degradation on FPGA Design Security. ISVLSI 2011: 230-235
e1		David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens (Eds.): Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011. ACM 2011, isbn 978-1-4503-0667-6
	2010
j27		Gabriel H. Loh, Yuan Xie: 3D Stacked Microprocessor: Are We There Yet? IEEE Micro 30(3): 60-64 (2010)
j26		Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie: Test-access mechanism optimization for core-based three-dimensional SOCs. Microelectronics Journal 41(10): 601-615 (2010)
j25		Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie: Design exploration of hybrid caches with disparate memory technologies. TACO 7(3): 15 (2010)
j24		Xiangyu Dong, Jishen Zhao, Yuan Xie: Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1959-1972 (2010)
j23		Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy: Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. VLSI Syst. 18(11): 1621-1624 (2010)
j22		Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Total Power Optimization for Combinational Logic Using Genetic Algorithms. Signal Processing Systems 58(2): 145-160 (2010)
c115		Jing Xie, Xiangyu Dong, Yuan Xie: 3D memory stacking for fast checkpointing/restore applications. 3DIC 2010: 1-6
c114		Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin: A 3D SoC design for H.264 application with on-chip DRAM stacking. 3DIC 2010: 1-6
c113		Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang: Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. ASP-DAC 2010: 169-174
c112		Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie: Energy and performance driven circuit design for emerging phase-change memory. ASP-DAC 2010: 193-198
c111		Yibo Chen, Yuan Xie, Yu Wang, Andrés Takach: Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment. ASP-DAC 2010: 689-694
c110		Yibo Chen, Yuan Xie, Yu Wang, Andrés Takach: Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library. ASP-DAC 2010: 781-786
c109		Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin: A customized design of DRAM controller for on-chip 3D DRAM stacking. CICC 2010: 1-4
c108		Jishen Zhao, Xiangyu Dong, Yuan Xie: Cost-aware three-dimensional (3D) many-core multiprocessor design. DAC 2010: 126-131
c107		Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li: Cost-driven 3D integration with interconnect layers. DAC 2010: 150-155
c106		Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie: Impact of process variations on emerging memristor. DAC 2010: 877-882
c105		Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie: Energy- and endurance-aware design of phase change memory caches. DATE 2010: 136-141
c104		Guangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li: A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. HPCA 2010: 1-12
c103		Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty: Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. ICCAD 2010: 471-476
c102		Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie: Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip. ICCAD 2010: 477-482
c101		Dimin Niu, Yiran Chen, Yuan Xie: Low-power dual-element memristor based memory design. ISLPED 2010: 25-30
c100		Yibo Chen, Jishen Zhao, Yuan Xie: 3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory. ISLPED 2010: 55-60
c99		Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu: Modeling TSV open defects in 3D-stacked DRAM. ITC 2010: 174-182
c98		Jin Ouyang, Yuan Xie: LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support. MICRO 2010: 409-420
c97		Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi: Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. SC 2010: 1-11
c96		Yuan Xie: Processor Architecture Design Using 3D Integration Technology. VLSI Design 2010: 446-451
	2009
j21		Yuan Xie, Yibo Chen: Statistical High-Level Synthesis under Process Variability. IEEE Design & Test of Computers 26(4): 78-87 (2009)
j20		David S. Kung, Yuan Xie: Guest Editors' Introduction: Opportunities and Challenges of 3D Integration. IEEE Design & Test of Computers 26(5): 4-5 (2009)
j19		Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Yuan Xie: Temperature-Aware NBTI Modeling Techniques in Digital Circuits. IEICE Transactions 92-C(6): 875-886 (2009)
j18		Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan: New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components. International Journal of Parallel Programming 37(4): 417-431 (2009)
j17		Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie: Scan-chain design and optimization for three-dimensional integrated circuits. JETC 5(2) (2009)
j16		Madhu Mutyam, Feng Wang, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin: Process-Variation-Aware Adaptive Cache Architecture and Management. IEEE Trans. Computers 58(7): 865-877 (2009)
j15		Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu: Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. IEEE Trans. Dependable Sec. Comput. 6(3): 202-216 (2009)
c95		Brent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott C. Smith: Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. 3DIC 2009: 1-5
c94		Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin: Arithmetic unit design using 180nm TSV-based 3D stacking technology. 3DIC 2009: 1-4
c93		Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwai Hung, Yuan Xie: 3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC). 3DIC 2009: 1-6
c92		Yibo Chen, Yuan Xie: Tolerating process variations in high-level synthesis using transparent latches. ASP-DAC 2009: 73-78
c91		Feng Wang, Yuan Xie, Andrés Takach: Variation-aware resource sharing and binding in behavioral synthesis. ASP-DAC 2009: 79-84
c90		Xiangyu Dong, Yuan Xie: System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs). ASP-DAC 2009: 234-241
c89		Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan: A framework for estimating NBTI degradation of microarchitectural components. ASP-DAC 2009: 455-460
c88		Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan: A criticality-driven microarchitectural three dimensional (3D) floorplanner. ASP-DAC 2009: 763-768
c87		Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang, Yuan Xie, Frank Mueller: CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. CASES 2009: 175-184
c86		Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang: Gate replacement techniques for simultaneous leakage and aging optimization. DATE 2009: 328-333
c85		Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yuan Xie: Power and performance of read-write aware Hybrid Caches with non-volatile memories. DATE 2009: 737-742
c84		Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen: A novel architecture of the 3D stacked MRAM L2 cache for CMPs. HPCA 2009: 239-249
c83		Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie: Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning. ICCAD 2009: 164-171
c82		Xiangyu Dong, Norman P. Jouppi, Yuan Xie: PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM. ICCAD 2009: 269-275
c81		Brandon Noia, Krishnendu Chakrabarty, Yuan Xie: Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs. ICCD 2009: 70-77
c80		Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Vijay Narayanan, Yuan Xie: 3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis. ICCD 2009: 254-259
c79		Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie: Hybrid cache architecture with disparate memory technologies. ISCA 2009: 34-45
c78		Guangyu Sun, Xiaoxia Wu, Yuan Xie: Exploration of 3D stacked L2 cache design for high performance and efficient thermal control. ISLPED 2009: 295-298
c77		Norman P. Jouppi, Yuan Xie: Emerging technologies and their impact on system design. ISLPED 2009: 427-428
c76		Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie, Yu Wang: NBTI-aware statistical circuit delay assessment. ISQED 2009: 13-18
c75		Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang: On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. ISQED 2009: 19-26
c74		Luca P. Carloni, Partha Pande, Yuan Xie: Networks-on-chip in emerging interconnect paradigms: Advantages and challenges. NOCS 2009: 93-102
c73		Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie: Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. SC 2009
	2008
j14		Yuan Xie, Jason Cong, Paul D. Franzon: Editorial: Special issue on 3D integrated circuits and microarchitectures. JETC 4(4) (2008)
j13		Suresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari: Toward Increasing FPGA Lifetime. IEEE Trans. Dependable Sec. Comput. 5(2): 115-127 (2008)
j12		Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Design Space Exploration for 3-D Cache. IEEE Trans. VLSI Syst. 16(4): 444-455 (2008)
j11		Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie: Case Study of Reliability-Aware and Low-Power Design. IEEE Trans. VLSI Syst. 16(7): 861-873 (2008)
c72		Feng Wang, Xiaoxia Wu, Yuan Xie: Variability-driven module selection with joint design time optimization and post-silicon tuning. ASP-DAC 2008: 2-9
c71		Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Helen Li, Yiran Chen: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. DAC 2008: 554-559
c70		Feng Wang, Guangyu Sun, Yuan Xie: A Variation Aware High Level Synthesis Framework. DATE 2008: 1063-1068
c69		Syed M. Alam, Mike Ignatowski, Yuan Xie: Technology, CAD tools, and designs for emerging 3D integration technology. ACM Great Lakes Symposium on VLSI 2008: 1-2
c68		Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim: A low-power phase change memory based hybrid cache architecture. ACM Great Lakes Symposium on VLSI 2008: 395-398
c67		Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie, Vijaykrishnan Narayanan: Thermal-aware reliability analysis for platform FPGAs. ICCAD 2008: 722-727
c66		Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie: Comparative analysis of NBTI effects on low power and high performance flip-flops. ICCD 2008: 200-205
c65		Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie: Test-access mechanism optimization for core-based three-dimensional SOCs. ICCD 2008: 212-218
c64		Feng Wang, Yuan Xie: Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations. IPDPS 2008: 1-5
c63		Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das: MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA 2008: 251-261
c62		Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, Kenan Unlu: Hierarchical Soft Error Estimation Tool (HSEET). ISQED 2008: 680-683
c61		Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie: Test-Access Solutions for Three-Dimensional SOCs. ITC 2008: 1
c60		Hai Lin, Guangyu Sun, Yunsi Fei, Yuan Xie, Anand Sivasubramaniam: Thermal-aware Design Considerations for Application-Specific Instruction Set Processor. SASP 2008: 63-68
c59		Xuebin Wu, Zhiyuan Yan, Yuan Xie: Two-dimensional crosstalk avoidance codes. SiPS 2008: 106-111
c58		Yibo Chen, Jin Ouyang, Yuan Xie: ILP-based scheme for timing variation-aware scheduling and resource binding. SoCC 2008: 27-30
c57		Jin Ouyang, Yuan Xie: Power optimization for FinFET-based circuits using genetic algorithms. SoCC 2008: 211-214
	2007
j10		Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: On-chip bus thermal analysis and optimisation. IET Computers & Digital Techniques 1(5): 590-599 (2007)
j9		Gabriel H. Loh, Yuan Xie, Bryan Black: Processor Design in 3D Die-Stacking Technologies. IEEE Micro 27(3): 31-48 (2007)
j8		Yuan Xie, Wayne Wolf, Haris Lekatsas: Code Decompression Unit Design for VLIW Embedded Processors. IEEE Trans. VLSI Syst. 15(8): 975-980 (2007)
j7		Chang Hong Lin, Yuan Xie, Wayne Wolf: Code Compression for VLIW Embedded Systems Using a Self-Generating Table. IEEE Trans. VLSI Syst. 15(10): 1160-1171 (2007)
j6		Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reliability-aware Co-synthesis for Embedded Systems. VLSI Signal Processing 49(1): 87-99 (2007)
c56		Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie: Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. DATE 2007: 546-551
c55		Feng Wang, Yuan Xie, Hai Ju: A novel criticality computation method in statistical timing analysis. DATE 2007: 1611-1616
c54		Feng Wang, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan: Variation-aware task allocation and scheduling for MPSoC. ICCAD 2007: 598-603
c53		Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan: FPGA routing architecture analysis under variations. ICCD 2007: 152-157
c52		Xiaoxia Wu, Paul Falkenstern, Yuan Xie: Scan chain design for three-dimensional integrated circuits (3D ICs). ICCD 2007: 208-214
c51		Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das: A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA 2007: 138-149
c50		Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie: Modeling of PMOS NBTI Effect Considering Temperature Variation. ISQED 2007: 139-144
c49		Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Analysis of CAM Cells. ISQED 2007: 333-338
c48		Krishnan Ramakrishnan, R. Rajaraman, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Impact on SER of Combinational Circuits. ISQED 2007: 911-916
c47		Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie: A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. PATMOS 2007: 160-170
c46		Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Architecting Microprocessor Components in 3D Design Space. VLSI Design 2007: 103-108
c45		Feng Wang, Yuan Xie, R. Rajaraman, Balaji Vaidyanathan: Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. VLSI Design 2007: 165-170
i3		Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Thermal-Aware Task Allocation and Scheduling for Embedded Systems. CoRR abs/0710.4660 (2007)
i2		Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie: Reliability-Centric High-Level Synthesis. CoRR abs/0710.4684 (2007)
i1		Yuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network. CoRR abs/0710.4731 (2007)
	2006
j5		Narayanan Vijaykrishnan, Yuan Xie: Reliability Concerns in Embedded System Designs. IEEE Computer 39(1): 118-120 (2006)
j4		Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein: Design space exploration for 3D architectures. JETC 2(2): 65-103 (2006)
j3		Yuan Xie, Wayne Wolf, Haris Lekatsas: Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding. IEEE Trans. VLSI Syst. 14(5): 525-536 (2006)
j2		Yuan Xie, Wei-Lun Hung: Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design. VLSI Signal Processing 45(3): 177-189 (2006)
c44		Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan, Rong Luo: Leakage Optimized DECAP Design for FPGAs. APCCAS 2006: 960-963
c43		Ozcan Ozturk, Feng Wang, Mahmut T. Kandemir, Yuan Xie: Optimal topology exploration for application-specific 3D architectures. ASP-DAC 2006: 390-395
c42		Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari: FLAW: FPGA lifetime awareness. DAC 2006: 630-635
c41		Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: On-chip bus thermal analysis and optimization. DATE 2006: 850-855
c40		Wei-Lun Hung, Xiaoxia Wu, Yuan Xie: Guaranteeing performance yield in high-level synthesis. ICCAD 2006: 303-309
c39		Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir: Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. ISCA 2006: 130-141
c38		Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ISQED 2006: 98-104
c37		Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie: Reliability-Aware SOC Voltage Islands Partition and Floorplan. ISVLSI 2006: 343-348
c36		Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie: Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI 2006: 355-360
c35		Feng Wang, Yuan Xie, Kerry Bernstein, Yan Luo: Dependability Analysis of Nano-scale FinFET circuits. ISVLSI 2006: 399-404
c34		Xiaoxia Wu, Feng Wang, Yuan Xie: Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design. SoCC 2006: 91-92
c33		Balaji Vaidyanathan, Yuan Xie: Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression. SoCC 2006: 193-196
c32		Qian Ding, Rong Luo, Hui Wang, Huazhong Yang, Yuan Xie: Modeling the Impact of Process Variation on Critical Charge Distribution. SoCC 2006: 243-246
c31		R. Rajaraman, Jungsub Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. VLSI Design 2006: 499-502
c30		Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal: A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. VLSI Design 2006: 657-664
	2005
c29		Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Designing reliable circuit in the presence of soft errors. ASP-DAC 2005: 1
c28		Shengqi Yang, Wayne Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie: Low-leakage robust SRAM cell design for sub-100nm technologies. ASP-DAC 2005: 539-544
c27		John Conner, Yuan Xie, Mahmut T. Kandemir, Robert P. Dick, Greg M. Link: FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection. ASP-DAC 2005: 709-712
c26		Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie: Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. DATE 2005: 64-69
c25		Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network. DATE 2005: 230-231
c24		Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Thermal-Aware Task Allocation and Scheduling for Embedded Systems. DATE 2005: 898-899
c23		Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie: Reliability-Centric High-Level Synthesis. DATE 2005: 1258-1263
c22		Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Three-Dimensional Cache Design Exploration Using 3DCacti. ICCD 2005: 519-524
c21		Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie: Temperature-Sensitive Loop Parallelization for Chip Multiprocessors. ICCD 2005: 677-682
c20		Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner: Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD 2005: 689-696
c19		Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung: An ILP Formulation for Reliability-Oriented High-Level Synthesis. ISQED 2005: 364-369
c18		Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung: Reliability-Centric Hardware/Software Co-Design. ISQED 2005: 375-380
c17		Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin: Thermal-Aware Floorplanning Using Genetic Algorithms. ISQED 2005: 634-639
c16		Daniel Hostetler, Yuan Xie: Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters. ISVLSI 2005: 186-191
c15		Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang: Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. VLSI Design 2005: 165-170
c14		Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. VLSI Design 2005: 374-379
	2004
c13		Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reliability-Aware Co-Synthesis for Embedded Systems. ASAP 2004: 41-50
c12		Chang Hong Lin, Yuan Xie, Wayne Wolf: LZW-Based Code Compression for VLIW Embedded Systems. DATE 2004: 76-81
c11		Wei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Design of a nanosensor array architecture. ACM Great Lakes Symposium on VLSI 2004: 298-303
c10		Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin: Improving soft-error tolerance of FPGA configuration bits. ICCAD 2004: 107-110
c9		Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. ICCD 2004: 430-437
c8		Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: The Effect of Threshold Voltages on the Soft Error Rate. ISQED 2004: 503-508
	2003
j1		Yuan Xie, Jiang Xu, Wayne Wolf: Augmenting Platform-Based Design with Synthesis Tools. Journal of Circuits, Systems, and Computers 12(2): 125-142 (2003)
c7		Yuan Xie, Wayne Wolf, Haris Lekatsas: Profile-Driven Selective Code Compression. DATE 2003: 10462-10467
c6		Yuan Xie, Wayne Wolf, Haris Lekatsas: Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding. DCC 2003: 382-391
	2002
c5		Haris Lekatsas, Wayne Wolf, Yuan Xie: Code Compression for VLIW Processors Using Variable-to-Fixed Coding. ISSS 2002: 138-143
	2001
c4		Yuan Xie, Wayne Wolf: Allocation and scheduling of conditional task graph in hardware/software co-synthesis. DATE 2001: 620-625
c3		Yuan Xie, Haris Lekatsas, Wayne Wolf: Code Compression for VLIW Processors. Data Compression Conference 2001: 525
c2		Yuan Xie, Wayne Wolf, Haris Lekatsas: A code decompression architecture for VLIW processors. MICRO 2001: 66-75
	2000
c1		Yuan Xie, Wayne Wolf: Co-synthesis with custom ASICs. ASP-DAC 2000: 129-134

Coauthor Index

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