Jingling Xue

Xinwei Xie, Jingling Xue, Jie Zhang: Acculock: accurate and efficient detection of data races. Softw., Pract. Exper. 43(5): 543-576 (2013)

Huimin Cui, Qing Yi, Jingling Xue, Xiaobing Feng: Layout-oblivious compiler optimization for matrix computations. TACO 9(4): 35 (2013)

Lin Gao, Lian Li, Jingling Xue, Pen-Chung Yew: SEED: A Statically Greedy and Dynamically Adaptive Approach for Speculative Loop Execution. IEEE Trans. Computers 62(5): 1004-1016 (2013)

Qing Wan, Hui Wu, Jingling Xue: Scratchpad Memory aware task scheduling with minimum number of preemptions on a single processor. ASP-DAC 2013: 741-748

Yi Lu, Lei Shang, Xinwei Xie, Jingling Xue: An Incremental Points-to Analysis with CFL-Reachability. CC 2013: 61-81

Yulei Sui, Yue Li, Jingling Xue: Query-directed adaptive heap cloning for optimizing compilers. CGO 2013: 1-11

Yi Lu, John Potter, Jingling Xue: Structural Lock Correlation with Ownership Types. ESOP 2013: 391-410

Yang Yang, Huimin Cui, Xiaobing Feng, Jingling Xue: A Hybrid Circular Queue Method for Iterative Stencil Computations on GPUs. J. Comput. Sci. Technol. 27(1): 57-74 (2012)

Peng Di, Hui Wu, Jingling Xue, Feng Wang, Canqun Yang: Parallelizing SOR for GPGPUs using alternate loop tiling. Parallel Computing 38(6-7): 310-328 (2012)

Xuejun Yang, Li Wang, Jingling Xue, Qingbo Wu: Comparability Graph Coloring for Optimizing Utilization of Software-Managed Stream Register Files for Stream Processors. TACO 9(1): 5 (2012)

Huimin Cui, Jingling Xue, Lei Wang, Yang Yang, Xiaobing Feng, Dongrui Fan: Extendable pattern-oriented optimization directives. TACO 9(3): 14 (2012)

Xuejun Yang, Zhiyuan Wang, Jingling Xue, Yun Zhou: The Reliability Wall for Exascale Supercomputing. IEEE Trans. Computers 61(6): 767-779 (2012)

Li Wang, Jingling Xue, Xuejun Yang: Optimizing modulo scheduling to achieve reuse and concurrency for stream processors. The Journal of Supercomputing 59(3): 1229-1251 (2012)

Duo Liu, Yi Wang, Zili Shao, Minyi Guo, Jingling Xue: Optimally Maximizing Iteration-Level Loop Parallelism. IEEE Trans. Parallel Distrib. Syst. 23(3): 564-572 (2012)

Huimin Cui, Qing Yi, Jingling Xue, Xiaobing Feng: Layout-oblivious optimization for matrix computations. PACT 2012: 429-430

Yi Lu, John Potter, Jingling Xue: Ownership Types for Object Synchronisation. APLAS 2012: 18-33

Lei Shang, Xinwei Xie, Jingling Xue: On-demand dynamic summary-based points-to analysis. CGO 2012: 264-274

Yi Lu, John Potter, Chenyi Zhang, Jingling Xue: A Type and Effect System for Determinism in Multithreaded Programs. ESOP 2012: 518-538

Peng Di, Ding Ye, Yu Su, Yulei Sui, Jingling Xue: Automatic Parallelization of Tiled Loop Nests with Enhanced Fine-Grained Parallelism on GPUs. ICPP 2012: 350-359

Qiang Wu, Canqun Yang, Feng Wang, Jingling Xue: A Fast Parallel Implementation of Molecular Dynamics with the Morse Potential on a Heterogeneous Petascale Supercomputer. IPDPS Workshops 2012: 140-149

Huimin Cui, Qing Yi, Jingling Xue, Lei Wang, Yang Yang, Xiaobing Feng: A Highly Parallel Reuse Distance Analysis Algorithm on GPUs. IPDPS 2012: 1080-1092

Yian Zhu, Yue Li, Jingling Xue, Tian Tan, Jialong Shi, Yang Shen, Chunyan Ma: What Is System Hang and How to Handle It. ISSRE 2012: 141-150

Yulei Sui, Ding Ye, Jingling Xue: Static memory leak detection using full-sparse value-flow analysis. ISSTA 2012: 254-264

Lei Shang, Yi Lu, Jingling Xue: Fast and precise points-to analysis with incremental CFL-reachability summarisation: preliminary experience. ASE 2012: 270-273

Qing Wan, Hui Wu, Jingling Xue: WCET-aware data selection and allocation for scratchpad memory. LCTES 2012: 41-50

Yong Guan, Jingling Xue: Leakage-Aware Modulo Scheduling for Embedded VLIW Processors. J. Comput. Sci. Technol. 26(3): 405-417 (2011)

Yulei Sui, Sen Ye, Jingling Xue, Pen-Chung Yew: SPAS: Scalable Path-Sensitive Pointer Analysis on Full-Sparse SSA. APLAS 2011: 155-171

Xuemeng Zhang, Hui Wu, Jingling Xue: An efficient heuristic for instruction scheduling on clustered vliw processors. CASES 2011: 35-44

Huimin Cui, Jingling Xue, Lei Wang, Yang Yang, Xiaobing Feng, Dongrui Fan: Extendable pattern-oriented optimization directives. CGO 2011: 107-118

Xinwei Xie, Jingling Xue: Acculock: Accurate and efficient detection of data races. CGO 2011: 201-212

Peng Di, Jingling Xue: Model-Driven Tile Size Selection for DOACROSS Loops on GPUs. Euro-Par (2) 2011: 401-412

Sabbir Mahmud, Hui Wu, Jingling Xue: Efficient Energy Balancing Aware Multiple Base Station Deployment for WSNs. EWSN 2011: 179-194

Huimin Cui, Lei Wang, Jingling Xue, Yang Yang, Xiaobing Feng: Automatic Library Generation for BLAS3 on GPUs. IPDPS 2011: 255-265

Anderson Kuei-An Ku, Jingling Xue, Yong Guan: Gather/scatter hardware support for accelerating Fast Fourier Transform. Journal of Systems Architecture - Embedded Systems Design 56(12): 667-684 (2010)

Lin Gao, Jingling Xue, Tin-Fook Ngai: Loop recreation for thread-level speculation on multicore processors. Softw., Pract. Exper. 40(1): 45-72 (2010)

Xuejun Yang, Ying Zhang, Xicheng Lu, Jingling Xue, Ian Rogers, Gen Li, Guibin Wang, Xudong Fang: Exploiting the reuse supplied by loop-dependent stream references for stream processors. TACO 7(2) (2010)

Lian Li, Jingling Xue, Jens Knoop: Scratchpad memory allocation for data aggregates via interval coloring in superperfect graphs. ACM Trans. Embedded Comput. Syst. 10(2): 28 (2010)

Xuejun Yang, Li Wang, Jingling Xue, Tao Tang, Xiaoguang Ren, Sen Ye: Improving scratchpad allocation with demand-driven data tiling. CASES 2010: 127-136

Hongtao Yu, Jingling Xue, Wei Huo, Xiaobing Feng, Zhaoqing Zhang: Level by level: making flow- and context-sensitive pointer analysis scalable for millions of lines of code. CGO 2010: 218-229

Li Wang, Jingling Xue, Xuejun Yang: Reuse-aware modulo scheduling for stream processors. DATE 2010: 1112-1117

Hui Wu, Jingling Xue, Sridevan Parameswaran: Optimal WCET-aware code selection for scratchpad memory. EMSOFT 2010: 59-68

Peng Di, Qing Wan, Xuemeng Zhang, Hui Wu, Jingling Xue: Toward Harnessing DOACROSS Parallelism for Multi-GPGPUs. ICPP 2010: 40-50

Wei Mi, Xiaobing Feng, Jingling Xue, Yao-Cang Jia: Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors. NPC 2010: 329-343

Wei Mi, Xiaobing Feng, Yao-Cang Jia, Li Chen, Jingling Xue: PARBLO: Page-Allocation-Based DRAM Row Buffer Locality Optimization. J. Comput. Sci. Technol. 24(6): 1086-1097 (2009)

Lian Li, Hui Feng, Jingling Xue: Compiler-directed scratchpad memory management via graph coloring. TACO 6(3) (2009)

Yi Lu, John Potter, Jingling Xue: Ownership Downgrading for Ownership Types. APLAS 2009: 144-160

Duo Liu, Zili Shao, Meng Wang, Minyi Guo, Jingling Xue: Optimal loop parallelization for maximizing iteration-level parallelism. CASES 2009: 67-76

Lin Gao, Lian Li, Jingling Xue, Tin-Fook Ngai: Exploiting Speculative TLP in Recursive Programs by Dynamic Thread Prediction. CC 2009: 78-93

Peng Di, Jingling Xue, Changjun Hu, Jingjing Zhou: A Cache-Efficient Parallel Gauss-Seidel Solver with Alternating Tiling. ICPADS 2009: 244-251

Xuejun Yang, Li Wang, Jingling Xue, Yu Deng, Ying Zhang: Comparability graph coloring for optimizing utilization of stream register files in stream processors. PPOPP 2009: 111-120

Bernhard Scholz, Bernd Burgstaller, Jingling Xue: Minimal placement of bank selection instructions for partitioned memory architectures. ACM Trans. Embedded Comput. Syst. 7(2) (2008)

Minyi Guo, Jingling Xue: Advances in high performance computing. The Journal of Supercomputing 43(2): 105-106 (2008)

Jingling Xue, Minyi Guo, Daming Wei: Improving the parallelism of iterative methods by aggressive loop fusion. The Journal of Supercomputing 43(2): 147-164 (2008)

Xuejun Yang, Ying Zhang, Jingling Xue, Ian Rogers, Gen Li, Guibin Wang: Exploiting loop-dependent stream reuse for stream processors. PACT 2008: 22-31

Anderson Kuei-An Ku, Jenny Yi-Chun Kuo, Jingling Xue: Hardware Support for Efficient Sparse Matrix Vector Multiplication. EUC (1) 2008: 37-43

Jenny Yi-Chun Kuo, Anderson Kuei-An Ku, Jingling Xue, Oliver Diessel, Usama Malik: ACS: An Addressless Configuration Support for efficient partial reconfigurations. FPT 2008: 161-168

Lin Gao, Quan Hoang Nguyen, Lian Li, Jingling Xue, Tin-Fook Ngai: Thread-Sensitive Modulo Scheduling for Multicore Processors. ICPP 2008: 132-140

Li Wang, Xuejun Yang, Jingling Xue, Yu Deng, Xiaobo Yan, Tao Tang, Quan Hoang Nguyen: Optimizing scientific application loops on stream processors. LCTES 2008: 161-170

Lian Li, Jingling Xue: Trace-based leakage energy optimisations at link time. Journal of Systems Architecture 53(1): 1-20 (2007)

Jingling Xue, Phung Hua Nguyen, John Potter: Interprocedural side-effect analysis for incomplete object-oriented software modules. Journal of Systems and Software 80(1): 92-105 (2007)

Xavier Vera, Björn Lisper, Jingling Xue: Data cache locking for tight timing calculations. ACM Trans. Embedded Comput. Syst. 7(1) (2007)

Lian Li, Hui Wu, Hui Feng, Jingling Xue: Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation. Asia-Pacific Computer Systems Architecture Conference 2007: 63-74

Yi Lu, John Potter, Jingling Xue: Validity Invariants and Effects. ECOOP 2007: 202-226

Lin Gao, Lian Li, Jingling Xue, Tin-Fook Ngai: Loop recreation for thread-level speculation. ICPADS 2007: 1-10

Lei Pan, Jingling Xue, Ming Kin Lai, Michael B. Dillencourt, Lubomir F. Bic: Toward Automatic Data Distribution for Migrating Computations. ICPP 2007: 27

Lian Li, Quan Hoang Nguyen, Jingling Xue: Scratchpad allocation for data aggregates in superperfect graphs. LCTES 2007: 207-216

Jingling Xue, Qiong Cai, Lin Gao: Partial dead code elimination on predicated code regions. Softw., Pract. Exper. 36(15): 1655-1685 (2006)

Jingling Xue, Jens Knoop: A Fresh Look at Partial Redundancy Elimination as a Maximum Flow Problem. Softwaretechnik-Trends 26(2) (2006)

Jingling Xue, Qiong Cai: A lifetime optimal algorithm for speculative PRE. TACO 3(2): 115-155 (2006)

Lian Li, Jingling Xue: Trace-Based Data Cache Leakage Reduction at Link Time. Asia-Pacific Computer Systems Architecture Conference 2006: 175-188

Bernhard Scholz, Bernd Burgstaller, Jingling Xue: Minimizing bank selection instructions for partitioned memory architecture. CASES 2006: 201-211

Jingling Xue, Jens Knoop: A Fresh Look at PRE as a Maximum Flow Problem. CC 2006: 139-154

Baoliu Ye, Minyi Guo, Jingling Xue: CoopStream: A Cooperative Cache Based Streaming Schedule Scheme for On-demand Media Services on Overlay Networks. ICPP 2006: 577-584

Hui Wu, Joxan Jaffar, Jingling Xue: Instruction Scheduling with Release Times and Deadlines on ILP Processors. RTCSA 2006: 51-60

Pen-Chung Yew, Jingling Xue: Forword. J. Comput. Sci. Technol. 20(5): 575-576 (2005)

Jingling Xue: Cache exploitation in embedded systems. J. Embedded Computing 1(4): 435-436 (2005)

Lian Li, Lin Gao, Jingling Xue: Memory Coloring: A Compiler Approach for Scratchpad Memory Management. IEEE PACT 2005: 329-338

Canqun Yang, Xuejun Yang, Jingling Xue: Improving the Performance of GCC by Exploiting IA-64 Architectural Features. Asia-Pacific Computer Systems Architecture Conference 2005: 236-251

Phung Hua Nguyen, Jingling Xue: Interprocedural Side-Effect Analysis and Optimisation in the Presence of Dynamic Class Loading. ACSC 2005: 9-18

Jingling Xue, Phung Hua Nguyen: Completeness Analysis for Incomplete Object-Oriented Programs. CC 2005: 271-286

Jingling Xue: Compiler-Directed Scratchpad Memory Management. ICESS 2005: 2

Weng-Long Chang, Michael (Shan-Hui) Ho, Minyi Guo, Xiaohong Jiang, Jingling Xue, Minglu Li: Fast Parallel DNA-Based Algorithms for Molecular Computation: Determining a Prime Number. ICITA (1) 2005: 447-452

Jingling Xue, Qingguang Huang, Minyi Guo: Enabling Loop Fusion and Tiling for Cache Performance by Fixing Fusion-Preventing Data Dependences. ICPP 2005: 107-115

Jingling Xue: Aggressive Loop Fusion for Improving Locality and Parallelism. ISPA 2005: 224-238

Thambipillai Srikanthan, Jingling Xue, Chip-Hong Chang (Eds.): Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings. Lecture Notes in Computer Science 3740, Springer 2005, isbn 3-540-29643-3

Jingling Xue, Xavier Vera: Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior. IEEE Trans. Computers 53(5): 547-566 (2004)

Phung Hua Nguyen, Jingling Xue: Strength Reduction for Loop-Invariant Types. ACSC 2004: 213-222

Budi Kurniawan, Jingling Xue: A Comparative Study of Web Application Design Models Using the Java Technologies. APWeb 2004: 711-721

Qiong Cai, Lin Gao, Jingling Xue: Region-Based Partial Dead Code Elimination on Predicated Code. CC 2004: 150-166

Lian Li, Jingling Xue: A trace-based binary compilation framework for energy-aware computing. LCTES 2004: 95-106

Pen-Chung Yew, Jingling Xue (Eds.): Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings. Lecture Notes in Computer Science 3189, Springer 2004, isbn 3-540-23003-3

Qiong Cai, Jingling Xue: Optimal and Efficient Speculation-Based Partial Redundancy Elimination. CGO 2003: 91-104

Qingguang Huang, Jingling Xue, Xavier Vera: Code Tiling for Improving the Cache Performance of PDE Solvers. ICPP 2003: 615-

Xavier Vera, Björn Lisper, Jingling Xue: Data Caches in Multitasking Hard Real-Time Systems. RTSS 2003: 154-165

Xavier Vera, Björn Lisper, Jingling Xue: Data cache locking for higher program predictability. SIGMETRICS 2003: 272-282

Jingling Xue, Patrick M. Lenders: Space-Time Equations for Non-Unimodular Mappings. Int. J. Comput. Math. 79(5): 555 (2002)

Patrick M. Lenders, Jingling Xue: Eigenvectors-based parallelisation of nested loops with affine dependences. Parallel Algorithms Appl. 17(3): 227-248 (2002)

Jingling Xue, Wentong Cai: Time-minimal tiling when rise is larger than zero. Parallel Computing 28(6): 915-939 (2002)

Xavier Vera, Jingling Xue: Let's Study Whole-Program Cache Behaviour Analytically. HPCA 2002: 175-186

Shiping Chen, Jingling Xue: Communication Overhead on Distributed Memory Machines. Scalable Computing: Practice and Experience 4(1) (2001)

Jingling Xue: Loop Tiling for Parallelism. Kluwer International Series in Engineering and Computer Science 575, Kluwer 2000, isbn 0-7923-7933-0

Peiyi Tang, Jingling Xue: Generating efficient tiled code for distributed memory machines. Parallel Computing 26(11): 1369-1410 (2000)

Shiping Chen, Jingling Xue: Partitioning and scheduling loops on NOWs. Computer Communications 22(11): 1017-1033 (1999)

Jingling Xue, Chua-Huang Huang: Reuse-Driven Tiling for Improving Data Locality. International Journal of Parallel Programming 26(6): 671-696 (1998)

Jingling Xue: Communication-Minimal Tiling of Uniform Dependence Loops. J. Parallel Distrib. Comput. 42(1): 42-59 (1997)

Jingling Xue: Unimodular Transformations of Non-Perfectly Nested Loops. Parallel Computing 22(12): 1621-1645 (1997)

Jingling Xue: On Tiling as a Loop Transformation. Parallel Processing Letters 7(4): 409-424 (1997)

Jingling Xue, Chua-Huang Huang: Reuse-Driven Tiling for Data Locality. LCPC 1997: 16-33

Jingling Xue: Transformations of Nested Loops with Non-Convex Iteration Spaces. Parallel Computing 22(3): 339-368 (1996)

Jingling Xue: Generalising the Unimodular Approach to Restructure Imperfectly Nested Loops. Parallel Processing Letters 6(3): 401-414 (1996)

Jingling Xue: Affine-by-Statement Transformations of Imperfectly Nested Loops. IPPS 1996: 34-38

Jingling Xue: Communication-Minimal Tiling of Uniform Dependence Loops. LCPC 1996: 330-349

Jingling Xue: Closed-form mapping conditions for the synthesis of linear processor arrays. VLSI Signal Processing 10(2): 181-199 (1995)

Jingling Xue: Constructing DO loops for non-convex iteration spaces in compiling for parallel machines. IPPS 1995: 364-368

Jingling Xue: Automating Non-Unimodular Loop Transformations for Massive Parallelism. Parallel Computing 20(5): 711-728 (1994)

Jingling Xue, Patrick M. Lenders: Avoiding Data Link and Computational Conflicts in Mapping Nested Loop Algorithms to Lower-Dimensional Processor Arrays. ICPADS 1994: 567-572

Jingling Xue: An Algorithm to Automate Non-Unimodular Transformations of Loop Nests. SPDP 1993: 512-521

Christian Lengauer, Jingling Xue: A systolic array for pyramidal algorithms. VLSI Signal Processing 4(1): 89 (1992)

Jingling Xue: On the Loading, Recovery and Access of Stationary Data in Systolic Arrays. CONPAR 1992: 259-264

Jingling Xue: Specifying control signals for Systolic Arrays by Uniform Recurrence Equations. Parallel Processing Letters 1: 83-93 (1991)

Christian Lengauer, Jingling Xue: A systolic array for pyramidal algorithms. VLSI Signal Processing 3(3): 237-257 (1991)

Jingling Xue, Christian Lengauer: Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations. Algorithms and Parallel VLSI Architectures 1991: 181-186

Jingling Xue, Xian-Long Hong: A new data structure for representing cell hierarchy in layout design. Computers & Graphics 12(3-4): 341-348 (1988)