Sudhakar Yalamanchili

Gregory Frederick Diamos, Haicheng Wu, Jin Wang, Ashwin Lele, Sudhakar Yalamanchili: Relational algorithms for multi-bulk-synchronous processors. PPOPP 2013: 301-302

Haicheng Wu, Gregory F. Diamos, Jin Wang, Si Li, Sudhakar Yalamanchili: Characterization and transformation of unstructured control flow in bulk synchronous GPU applications. IJHPCA 26(2): 170-185 (2012)

Andrew Kerr, Gregory Frederick Diamos, Sudhakar Yalamanchili: Dynamic compilation of data-parallel kernels for vector processors. CGO 2012: 23-32

Andrew Kerr, Eric Anger, Gilbert Hendry, Sudhakar Yalamanchili: Eiger: A framework for the automated synthesis of statistical performance models. HiPC 2012: 1-6

Jeffrey Young, Sudhakar Yalamanchili: Commodity Converged Fabrics for Global Address Spaces in Accelerator Clouds. HPCC-ICESS 2012: 303-310

Indrani Paul, Sudhakar Yalamanchili, Lizy K. John: Performance impact of virtual machine placement in a datacenter. IPCCC 2012: 424-431

Haicheng Wu, Gregory F. Diamos, Jin Wang, Srihari Cadambi, Sudhakar Yalamanchili, Srimat T. Chakradhar: Optimizing Data Warehousing Applications for GPUs Using Kernel Fusion/Fission. IPDPS Workshops 2012: 2433-2442

Naila Farooqui, Andrew Kerr, Greg Eisenhauer, Karsten Schwan, Sudhakar Yalamanchili: Lynx: A dynamic instrumentation system for data-parallel applications on GPGPU architectures. ISPASS 2012: 58-67

Haicheng Wu, Gregory Frederick Diamos, Srihari Cadambi, Sudhakar Yalamanchili: Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation. MICRO 2012: 107-118

Jun Wang, Jesse Beu, Sudhakar Yalamanchili, Tom Conte: Designing Configurable, Modifiable and Reusable Components for Simulation of Multicore Systems. SC Companion 2012: 472-476

Jeffrey Young, Haicheng Wu, Sudhakar Yalamanchili: Satisfying Data-Intensive Queries Using GPU Clusters. SC Companion 2012: 1314

Jeffrey S. Vetter, Richard Glassbrook, Jack Dongarra, Karsten Schwan, Bruce Loftis, Stephen McNally, Jeremy S. Meredith, James Rogers, Philip C. Roth, Kyle Spafford, Sudhakar Yalamanchili: Keeneland: Bringing Heterogeneous GPU Computing to the Computational Science Community. Computing in Science and Engineering 13(5): 90-95 (2011)

Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay: A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. IEEE Trans. VLSI Syst. 19(5): 809-817 (2011)

Syed Minhaj Hassan, Dhruv Choudhary, Mitchelle Rasquinha, Sudhakar Yalamanchili: Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments. PACT 2011: 187-188

Naila Farooqui, Andrew Kerr, Gregory Frederick Diamos, Sudhakar Yalamanchili, Karsten Schwan: A framework for dynamically instrumenting GPU compute applications within GPU Ocelot. GPGPU 2011: 9

Gregory Frederick Diamos, Benjamin Ashbaugh, Subramaniam Maiyuran, Andrew Kerr, Haicheng Wu, Sudhakar Yalamanchili: SIMD re-convergence at thread frontiers. MICRO 2011: 477-488

Sudhakar Yalamanchili: Interconnection Networks. Encyclopedia of Parallel Computing 2011: 964-975

Sudhakar Yalamanchili: Switching Techniques. Encyclopedia of Parallel Computing 2011: 1977-1989

Gregory Frederick Diamos, Andrew Kerr, Sudhakar Yalamanchili, Nathan Clark: Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems. PACT 2010: 353-364

Karsten Schwan, Ada Gavrilovska, Sudhakar Yalamanchili: HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors. ARCS 2010: 1

Andrew Kerr, Gregory F. Diamos, Sudhakar Yalamanchili: Modeling GPU-CPU workloads and systems. GPGPU 2010: 31-42

Jeffrey Young, Sudhakar Yalamanchili: Dynamic Partitioned Global Address Spaces for power efficient DRAM virtualization. Green Computing Conference 2010: 485-492

Gregory F. Diamos, Sudhakar Yalamanchili: Speculative execution on multi-GPU systems. IPDPS 2010: 1-12

Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili: An energy efficient cache design using spin torque transfer (STT) RAM. ISLPED 2010: 389-394

Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay: A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. ICCAD 2009: 474-477

Andrew Kerr, Gregory F. Diamos, Sudhakar Yalamanchili: A characterization and analysis of PTX kernels. IISWC 2009: 3-12

Dean L. Lewis, Sudhakar Yalamanchili, Hsien-Hsin S. Lee: High Performance Non-blocking Switch Design in 3D Die-Stacking Technology. ISVLSI 2009: 25-30

Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan: ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator. FCCM 2008: 265-268

Subramanian Ramaswamy, Sudhakar Yalamanchili: An Utilization Driven Framework for Energy Efficient Caches. HiPC 2008: 583-594

Gregory F. Diamos, Sudhakar Yalamanchili: Harmony: an execution model and runtime for heterogeneous many core systems. HPDC 2008: 197-200

Subramanian Ramaswamy, Sudhakar Yalamanchili: Customized Placement for High Performance Embedded Processor Caches. ARCS 2007: 69-82

Subramanian Ramaswamy, Sudhakar Yalamanchili: Improving cache efficiency via resizing + remapping. ICCD 2007: 47-54

Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili: MMR: A MultiMedia Router architecture to support hybrid workloads. J. Parallel Distrib. Comput. 66(2): 307-321 (2006)

Subramanian Ramaswamy, Jaswanth Sreeram, Sudhakar Yalamanchili, Krishna V. Palem: Data trace cache: an application specific cache architecture. SIGARCH Computer Architecture News 34(1): 11-18 (2006)

Subramanian Ramaswamy, Sudhakar Yalamanchili: Customizable Fault Tolerant Caches for Embedded Processors. ICCD 2006

Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili: Traffic Scheduling Solutions with QoS Support for an Input-Buffered MultiMedia Router. IEEE Trans. Parallel Distrib. Syst. 16(11): 1009-1021 (2005)

Krishna V. Palem, Lakshmi N. Chakrapani, Sudhakar Yalamanchili: A Framework for Compiler Driven Design Space Exploration for Embedded System Customization. ASIAN 2004: 395-406

Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West: ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers. FCCM 2004: 115-124

Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West: Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture. IPDPS 2003: 30

Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili: A Solution for Handling Hybrid Traffic in Clustered Environments: The MultiMedia Router MMR. IPDPS 2003: 197

Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili: A Hardware Approach to QoS Support in Cluster Environments: The Multimedia Router MMR. PDPTA 2003: 220-226

Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili: A new switch scheduling algorithm to improve QoS in the multimedia router. IEEE Workshop on Multimedia Signal Processing 2002: 376-379

Indrani Paul, Sudhakar Yalamanchili, José Duato: Algorithms for Switch-Scheduling in the Multimedia Router for LANs. HiPC 2002: 219-231

Sudhakar Yalamanchili: The Customization Landscape for Embedded Systems. HiPC 2002: 693-696

Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West: Architecture and Hardware for Scheduling Gigabit Packet Streams. Hot Interconnects 2002: 52-64

Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili: A multimedia router architecture to provide high performance and QoS guarantees to mixed traffic. ICME (1) 2002: 313-316

Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili: Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router. IPDPS 2002

Craig Ulmer, Sudhakar Yalamanchili: A Tunable Communications Library for Data Injection. PDPTA 2002: 1630-1636

Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili: A Cost-Effective Hardware Link Scheduling Algorithm for the Multimedia Router (MMR). ICN (2) 2001: 358-369

Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili: Tuning Buffer Size in the Multimedia Router (MMR). IPDPS 2001: 160

Young-Joo Suh, Binh Vien Dao, José Duato, Sudhakar Yalamanchili: Software-Based Rerouting for Fault-Tolerant Pipelined Communication. IEEE Trans. Parallel Distrib. Syst. 11(3): 193-211 (2000)

Young-Joo Suh, Sudhakar Yalamanchili: Configurable Algorithms for Complete Exchange in 2D Meshes. IEEE Trans. Parallel Distrib. Syst. 11(4): 337-356 (2000)

Damon S. Love, Sudhakar Yalamanchili, José Duato, Blanca Caminero, Francisco J. Quiles: Switch Scheduling in the Multimedia Router (MMR). IPDPS 2000: 5-12

Craig Ulmer, Sudhakar Yalamanchili: An Extensible Message Layer for High-Performance Clusters. PDPTA 2000

Binh Vien Dao, José Duato, Sudhakar Yalamanchili: Dynamically Configurable Message Flow Control for Fault-Tolerant Routing. IEEE Trans. Parallel Distrib. Syst. 10(1): 7-22 (1999)

Blanca Caminero, Francisco J. Quiles, José Duato, Damon S. Love, Sudhakar Yalamanchili: Performance Evaluation of the Multimedia Router with MPEG-2 Video Traffic. CANPC 1999: 62-76

Richard West, Raj Krishnamurthy, W. K. Norton, Karsten Schwan, Sudhakar Yalamanchili, Marcel-Catalin Rosu, V. Sarat: QUIC: A Quality of Service Network Interface Layer for Communication in NOWs. Heterogeneous Computing Workshop 1999: 199-208

José Duato, Sudhakar Yalamanchili, Blanca Caminero, Damon S. Love, Francisco J. Quiles: MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs. HPCA 1999: 300-309

Tsai Chi Huang, Sudhakar Yalamanchili, Roy W. Melton, Philip R. Bingham, Cecil O. Alford: Teaching Pipelining and Concurrency using Hardware Description Languages. MSE 1999: 55-56

Young-Joo Suh, Sudhakar Yalamanchili: All-To-All Communication with Minimum Start-Up Costs in 2D/3D Tori and Meshes. IEEE Trans. Parallel Distrib. Syst. 9(5): 442-458 (1998)

Daniela Rosu, Karsten Schwan, Sudhakar Yalamanchili: FARA - A Framework for Adaptive Resource Allocation in Complex Real-Time Systems. IEEE Real Time Technology and Applications Symposium 1998: 79-84

Sudhakar Yalamanchili, José Duato (Eds.): Parallel Computer Routing and Communication, Second International Workshop, PCRCW'97, Atlanta, Georgia, USA, June 26-27, 1997, Proceedings. Lecture Notes in Computer Science 1417, Springer 1998, isbn 3-540-64571-3

José Duato, Sudhakar Yalamanchili, Lionel M. Ni: Interconnection networks - an engineering approach. IEEE 1997, isbn 978-0-8186-7800-4, pp. I-XVIII, 1-515

Binh Vien Dao, Sudhakar Yalamanchili, José Duato: Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks. HPCA 1997: 343-352

Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchili, David E. Schimmel: Power Constrained Design of Multiprocessor Interconnection Networks. ICCD 1997: 408-416

José Duato, Pedro López, Sudhakar Yalamanchili: Deadlock- and Livelock-Free Routing Protocols for Wave Switching. IPPS 1997: 570-577

Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchili, David E. Schimmel: Power/Performance Trade-offs for Direct Networks. PCRCW 1997: 231-246

Daniela Rosu, Karsten Schwan, Sudhakar Yalamanchili, Rakesh Jha: On adaptive resource allocation for complex real-time application. RTSS 1997: 320-329

Sudhakar Yalamanchili, Todd Carpenter: Paradigms for Modeling and Simulation of Multiprocessor Architectures. Int. Journal in Computer Simulation 6(1): 137- (1996)

Patrick T. Gaughan, Binh Vien Dao, Sudhakar Yalamanchili, David E. Schimmel: Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks. IEEE Trans. Computers 45(6): 651-665 (1996)

Hari Lalgudi, Ian F. Akyildiz, Sudhakar Yalamanchili: Augmented Binary Hypercube: A New Architecture for Processor Management. IEEE Trans. Computers 45(8): 980-984 (1996)

José Duato, Pedro López, Federico Silla, Sudhakar Yalamanchili: A High Performance Router Architecture for Interconnection Networks. ICPP, Vol. 1 1996: 61-68

Young-Joo Suh, Sudhakar Yalamanchili: Algorithms for All-to-All Personalized Exchange in 2D and 3D Tori. IPPS 1996: 808-814

Sudhakar Yalamanchili, Lynn E. Te Winkel, David L. Perschbacher, Belle Shenoy: Partitioning and mapping in embedded multiprocessor architectures in the presence of constraints. Concurrency - Practice and Experience 7(3): 167-189 (1995)

Patrick T. Gaughan, Sudhakar Yalamanchili: A Performance Model of Pipelined K-ary n-cubes. IEEE Trans. Computers 44(8): 1059-1063 (1995)

Hatem Sellami, Sudhakar Yalamanchili: Parallelism in Sequential Multiprocessor Simulation Models: A Case Study. ACM Trans. Model. Comput. Simul. 5(2): 101-128 (1995)

Patrick T. Gaughan, Sudhakar Yalamanchili: A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks. IEEE Trans. Parallel Distrib. Syst. 6(5): 482-497 (1995)

Young-Joo Suh, Binh Vien Dao, José Duato, Sudhakar Yalamanchili: Software Based Fault-Tolerant Oblivious Routing in Pipelined Networks. ICPP (1) 1995: 101-105

Hatem Sellami, Sudhakar Yalamanchili: Time scale combining of conservative parallel discrete event simulations. IPPS 1995: 599-

Binh Vien Dao, José Duato, Sudhakar Yalamanchili: Configurable Flow Control Mechanisms for Fault-Tolerant Routing. ISCA 1995: 220-229

Christopher H. de Castro, Sudhakar Yalamanchili: Partitioning Coarse-Grain Signal Flow Graphs for Heterogeneous DSP Architectures. Int. Journal in Computer Simulation 4(4): 0- (1994)

Eileen Tien Lin, Edward Omiecinski, Sudhakar Yalamanchili: Large Join Optimization on a Hypercube Multiprocessor. IEEE Trans. Knowl. Data Eng. 6(2): 304-315 (1994)

José Duato, V. B. Dao, Patrick T. Gaughan, Sudhakar Yalamanchili: Scouting: Fully Adaptive, Deadlock-Free Routing in Faulty Pipelined Networks. ICPADS 1994: 608-613

James D. Allen, Patrick T. Gaughan, David E. Schimmel, Sudhakar Yalamanchili: Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers. ISCA 1994: 278-288

Hatem Sellami, James D. Allen, David E. Schimmel, Sudhakar Yalamanchili: Simulation of Marked Graphs on SIMD Architectures Using Efficient Memory Management. MASCOTS 1994: 343-348

Patrick T. Gaughan, Sudhakar Yalamanchili: Adaptive Routing Protocols for Hypercube Interconnection Networks. IEEE Computer 26(5): 12-23 (1993)

Patrick T. Gaughan, Sudhakar Yalamanchili: Analytical Models of Bandwidth Allocation in Pipelined k-ary n-cubes. IPPS 1993: 395-400

Hatem Sellami, Sudhakar Yalamanchili: Partitioning and Mapping a Class of Parallel Multiprocessor Simulation Models. SPDP 1993: 360-367

Sudhakar Yalamanchili, Lynn E. Te Winkel, David L. Perschbacher, Belle Shenoy: Genie: An Environment for Partitioning and Mapping in Embedded Multiprocessors. SPDP 1993: 522-529

Eileen Tien Lin, Edward Omiecinski, Sudhakar Yalamanchili: Parallel Optimization and Execution of Large Join Queries. FGCS 1992: 907-914

Ajay Mohindra, Sudhakar Yalamanchili: Dominant Representations: A Paradigm for Mapping Parallel Computations. IPPS 1992: 67-71

Patrick T. Gaughan, Sudhakar Yalamanchili: Pipelined Circuit-Switching: A Fault-Tolerant Variant of Wormhole Routing. SPDP 1992: 148-155

Steven D. Young, Sudhakar Yalamanchili: Adaptive routing in generalized hypercube architectures. SPDP 1991: 564-571

S. Y. Lee, Sudhakar Yalamanchili, Jake K. Aggarwal: Parallel image normalization on a mesh connected array processor. Pattern Recognition 20(1): 115-124 (1987)

Sudhakar Yalamanchili, Jake K. Aggarwal: A Characterization and Analysis of Parallel Processor Interconnection Networks. IEEE Trans. Computers 36(6): 680-691 (1987)

Sudhakar Yalamanchili, Jake K. Aggarwal: Reconfiguration Strategies for Parallel Architectures. IEEE Computer 18(12): 44-61 (1985)

Sudhakar Yalamanchili, Jake K. Aggarwal: Analysis of a model for parallel image processing. Pattern Recognition 18(1): 1-16 (1985)

Sudhakar Yalamanchili, Jake K. Aggarwal: A system organization for parallel image processing. Pattern Recognition 18(1): 17-29 (1985)

Sudhakar Yalamanchili, Miroslaw Malek, Jake K. Aggarwal: Workstations in a Local Area Network Environment. IEEE Computer 17(11): 74-86 (1984)

Sudhakar Yalamanchili, Jake K. Aggarwal: Algebraic Properties of some Parallel Processor Interconnection Networks. ICDE 1984: 611-618