Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Koichi Yamaguchi
2010 – today
- 2013
[c10]Gerrit den Besten, Koichi Yamaguchi: Session 23 overview: Short-reach links, XCVR techniques, & PLLs. ISSCC 2013: 398-399- [c9]Ken'ichiro Hijioka, Masaharu Matsudaira, Koichi Yamaguchi, Masayuki Mizuno: A 5.5Gb/s 5mm contactless interface containing a 50Mb/s bidirectional sub-channel employing common-mode OOK signaling. ISSCC 2013: 406-407
- 2011
- [j6]Koichi Yamaguchi, Masayuki Mizuno: Dicode Partial Response Signaling over Inductively-Coupled Channel. IEICE Transactions 94-C(4): 613-618 (2011)
- [j5]Koichi Yamaguchi, Masayuki Mizuno: A Duobinary Signaling for Asymmetric Multi-Chip Communication. IEICE Transactions 94-C(4): 619-626 (2011)
- 2010
- [j4]Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno: A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors. J. Solid-State Circuits 45(1): 15-22 (2010)
- [c8]Tsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Hideyuki Sugita, Yoichi Yoshida, Masayuki Mizuno, Tadahiro Kuroda: A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. CICC 2010: 1-4
- [c7]Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno: A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS. ISSCC 2010: 162-163
- [c6]Naresh R. Shanbhag, Koichi Yamaguchi, Robert Payne: Energy-efficient high-speed interfaces. ISSCC 2010: 524-525
2000 – 2009
- 2009
- [c5]Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno: A chip-stacked memory for on-chip SRAM-rich SoCs and processors. ISSCC 2009: 60-61
- [c4]Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama: A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery. ISSCC 2009: 192-193
- [c3]Kazuhisa Sunaga, Hideyuki Sugita, Koichi Yamaguchi, Kazumasa Suzuki: An 18Gb/s duobinary receiver with a CDR-assisted DFE. ISSCC 2009: 274-275
- 2007
- [j3]Naoki Kakuda, Shiro Tsukamoto, Akira Ishii, Katsutoshi Fujiwara, Toshikazu Ebisuzaki, Koichi Yamaguchi, Yasuhiko Arakawa: Surface reconstructions on Sb-irradiated GaAs(001) formed by molecular beam epitaxy. Microelectronics Journal 38(4-5): 620-624 (2007)
- 2001
- [j2]Naoki Kobayashi, Takaaki Hosoya, Michito Adachi, Tamami Haku, Koichi Yamaguchi: Virtual MR microscopy for unruptured aneurysm. Computer Methods and Programs in Biomedicine 66(1): 99-103 (2001)
1990 – 1999
- 1998
- [j1]Masahide Naemura, Atsushi Fukuda, Yasunobu Mizutani, Yoshinori Izumi, Koichi Yamaguchi, Yuichi Ninomiya: Detection of image orientation with mathematical morphology and orientation-adaptive image processing for antialiasing. Systems and Computers in Japan 29(6): 16-27 (1998)
1970 – 1979
- 1974
- [c2]Randall L. Frank, Koichi Yamaguchi: A model for a generalized data access method. AFIPS National Computer Conference 1974: 45-52
- [c1]Koichi Yamaguchi, Alan G. Merten: Methodology for Transferring Programs and Data. SIGMOD Workshop, Vol. 1 1974: 141-155
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-04-09 21:22 CEST by the dblp team