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Katsuhiro Yamazaki
2010 – today
- 2012
[i2]Truong Vinh Truong Duy, Katsuhiro Yamazaki, Kosai Ikegami, Shigeru Oyanagi: Hybrid MPI-OpenMP Paradigm on SMP Clusters: MPEG-2 Encoder and N-Body Simulation. CoRR abs/1211.2292 (2012)- [i1]Truong Vinh Truong Duy, Katsuhiro Yamazaki, Shigeru Oyanagi: Performance Evaluation of Treecode Algorithm for N-Body Simulation Using GridRPC System. CoRR abs/1211.2293 (2012)
2000 – 2009
- 2009
- [j2]Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi: Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate. IEICE Transactions 92-D(10): 2034-2042 (2009)
- 2008
- [c10]Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi: Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding. FCCM 2008: 271-272
- [c9]Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi: Three-stage pipeline implementation for SHA2 using data forwarding. FPL 2008: 29-34
- 2006
- [c8]Tran Minh Quang, Shigeru Oyanagi, Katsuhiro Yamazaki: ExMiner: An Efficient Algorithm for Mining Top-K Frequent Patterns. ADMA 2006: 436-447
- [c7]Tran Minh Quang, Shigeru Oyanagi, Katsuhiro Yamazaki: Mining the K-Most Interesting Frequent Patterns Sequentially. IDEAL 2006: 620-628
- 2004
- [j1]Tran Cong So, Shigeru Oyanagi, Katsuhiro Yamazaki: Speculative Selection Routing in 2D Torus Network. IEICE Transactions 87-D(7): 1666-1673 (2004)
1990 – 1999
- 1999
- [c6]Akira Uejima, Katsuhiro Yamazaki: Parallel Radiosity: Evaluation of Parallel Form Factor Calculations and a Static Load Balancing Algorithm. ISHPC 1999: 181-193
- 1998
- [c5]
- 1992
- [c4]Kenzo Okuda, Katsuhiro Yamazaki: An Application of Case-Based Reasoning for Fault Restoration Support in Electric Power Systems. IFIP Congress (3) 1992: 273-279
1980 – 1989
- 1986
- [c3]Katsuhiro Yamazaki, Takanobu Baba, Kenzo Okuda, Hiroyuki Kanai: Architectural Evaluation and Improvement of a Universal Host Computer MUNAP. IFIP Congress 1986: 779-784
- 1983
- [c2]Takanobu Baba, Katsuhiro Yamazaki, Nobuyuki Hashimoto, Hiroyuki Kanai, Kenzo Okuda, Kazuhiko Hashimoto: Hierarchical Micro-Architectures of a Two-Level Microprogrammed Multiprocessor Computer. ICPP 1983: 478-485
- 1980
- [c1]Kiyoshi Shibayama, Shinji Tomita, Hiroshi Hagiwara, Katsuhiro Yamazaki, Toshiaki Kitamura: Performance Evaluation and Improvement of a Dynamically Microprogrammable Computer with Low-Level Parallelism. IFIP Congress 1980: 181-186
Coauthor Index
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last updated on 2012-12-02 21:25 CET by the dblp team