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Chia-Lin Yang
2010 – today
- 2013
[c44]Ren-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen: DuraCache: a durable SSD cache using MLC NAND flash. DAC 2013: 166- 2012
- [c43]Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Naehyuck Chang: Memory access aware power gating for MPSoCs. ASP-DAC 2012: 121-126
- [c42]Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, Cheng-Yuan Michael Wang: Age-based PCM wear leveling with nearly zero search cost. DAC 2012: 453-458
- [c41]Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen: Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs. ICCAD 2012: 458-465
- [c40]Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang: SECRET: Selective error correction for refresh energy reduction in DRAMs. ICCD 2012: 67-74
- [c39]Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng: A cycle-level SIMT-GPU simulation framework. ISPASS 2012: 114-115
- 2011
- [j19]James C. Chen, Kou-Huang Chen, Chien-Hsin Lin, Chia-Wen Chen, Chia-Lin Yang: A Study of a Heuristic Capacity Planning Algorithm for Weapon Production System. IJEBM 9(1): 46-57 (2011)
- [j18]Po-Han Wang, Chia-Lin Yang, Yen-Ming Chen, Yu-Jung Cheng: Power gating strategies on GPUs. TACO 8(3): 13 (2011)
- [j17]Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen: TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems. IEEE Trans. Computers 60(6): 767-782 (2011)
- [j16]Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang: Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling. IEEE Trans. on CAD of Integrated Circuits and Systems 30(9): 1293-1306 (2011)
- [c38]Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang: A SAT-based routing algorithm for cross-referencing biochips. SLIP 2011: 1-7
- 2010
- [c37]Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang: PM-COSYN: PE and memory co-synthesis for MPSoCs. DATE 2010: 1590-1595
- [c36]Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang: Hierarchical memory scheduling for multimedia MPSoCs. ICCAD 2010: 190-196
- [c35]Ren-Shuo Liu, Yun-Cheng Tsai, Chia-Lin Yang: Parallelization and characterization of GARCH option pricing on GPUs. IISWC 2010: 1-10
- [c34]Sangyoung Park, Jian-Jia Chen, Donghwa Shin, Younghyun Kim, Chia-Lin Yang, Naehyuck Chang: Dynamic thermal management for networked embedded systems under harsh ambient temperature variation. ISLPED 2010: 289-294
- [c33]Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang: Memory Latency Reduction via Thread Throttling. MICRO 2010: 53-64
2000 – 2009
- 2009
- [j15]Po-Han Wang, Yen-Ming Chen, Chia-Lin Yang, Yu-Jung Cheng: A Predictive Shutdown Technique for GPU Shader Processors. Computer Architecture Letters 8(1): 9-12 (2009)
- [j14]Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang: An architectural co-synthesis algorithm for energy-aware Network-on-Chip design. Journal of Systems Architecture - Embedded Systems Design 55(5-6): 299-309 (2009)
- [j13]Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang: A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 28(9): 1295-1306 (2009)
- [j12]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: T-trees: A tree-based representation for temporal and three-dimensional floorplanning. ACM Trans. Design Autom. Electr. Syst. 14(4) (2009)
- [j11]Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin: Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. ACM Trans. Design Autom. Electr. Syst. 14(4) (2009)
- [j10]Sung-Wen Wang, Shu-Sian Yang, Hong-Ming Chen, Chia-Lin Yang, Ja-Ling Wu: A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters. Signal Processing Systems 57(2): 195-211 (2009)
- [c32]Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu: Thermal modeling for 3D-ICs with integrated microchannel cooling. ICCAD 2009: 256-263
- [c31]Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King: PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. ISLPED 2009: 93-98
- 2008
- [j9]Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang: Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 643-653 (2008)
- [j8]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1928-1941 (2008)
- [j7]Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng: Energy-Aware Flash Memory Management in Virtual Memory System. IEEE Trans. VLSI Syst. 16(8): 952-964 (2008)
- [c30]Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang: A progressive-ILP based routing algorithm for cross-referencing biochips. DAC 2008: 284-289
- 2007
- [j6]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. JETC 3(3) (2007)
- [j5]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Temporal floorplanning using the three-dimensional transitive closure subGraph. ACM Trans. Design Autom. Electr. Syst. 12(4) (2007)
- [c29]Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen: Cache leakage control mechanism for hard real-time systems. CASES 2007: 248-256
- [c28]Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King: Energy-efficient real-time task scheduling with task rejection. DATE 2007: 1629-1634
- [c27]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. ICCAD 2007: 752-757
- [c26]Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen: 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. ICME 2007: 9
- [c25]Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. ISLPED 2007: 92-97
- [c24]Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang: Efficient obstacle-avoiding rectilinear steiner tree construction. ISPD 2007: 127-134
- [c23]Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su: An architectural co-synthesis algorithm for energy-aware network-on-chip design. SAC 2007: 680-684
- 2006
- [c22]Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen: Branch Behavior Characterization for Multimedia Applications. Asia-Pacific Computer Systems Architecture Conference 2006: 523-530
- [c21]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Placement of digital microfluidic biochips using the t-tree formulation. DAC 2006: 931-934
- [c20]Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King: Hierarchical value cache encoding for off-chip data bus. ISLPED 2006: 143-146
- [c19]Hung-Wei Tseng, Han-Lin Li, Chia-Lin Yang: An energy-efficient virtual memory system with flash memory as the secondary storage. ISLPED 2006: 418-423
- [c18]Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang: A Space-Efficient Caching Mechanism for Flash-Memory Address Translation. ISORC 2006: 64-71
- 2005
- [j4]Chia-Lin Yang, Hong-Wei Tseng, Chia-Chiang Ho, Ja-Ling Wu: Software-Controlled Cache Architecture for Energy Efficiency. IEEE Trans. Circuits Syst. Video Techn. 15(5): 634-644 (2005)
- [c17]Chun-Yang Chen, Chia-Lin Yang, Shih-Hao Hung: Cache Leakage Management for Multi-programming Workloads. Asia-Pacific Computer Systems Architecture Conference 2005: 736-749
- [c16]Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang: Joint exploration of architectural and physical design spaces with thermal consideration. ISLPED 2005: 123-126
- [c15]Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen: Reconfigurable Platform for Content Science Research. RTCSA 2005: 481-486
- 2004
- [j3]Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee: Tolerating memory latency through push prefetching for pointer-intensive applications. TACO 1(4): 445-475 (2004)
- [j2]Yen-Jen Chang, Feipei Lai, Chia-Lin Yang: Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. IEEE Trans. VLSI Syst. 12(8): 827-836 (2004)
- [c14]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen: Temporal floorplanning using 3D-subTCG. ASP-DAC 2004: 725-730
- [c13]Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang: Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism. CODES+ISSS 2004: 134-139
- [c12]Yen-Jen Chang, Chia-Lin Yang, Feipei Lai: Value-Conscious Cache: Simple Technique for Reducing Cache Access Power. DATE 2004: 16-21
- [c11]Jian-Jia Chen, Heng-Ruey Hsu, Kai-Hsiang Chuang, Chia-Lin Yang, Ai-Chun Pang, Tei-Wei Kuo: Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations. ECRTS 2004: 101-108
- [c10]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Temporal floorplanning using the T-tree formulation. ICCAD 2004: 300-305
- [c9]Chia-Lin Yang, Chien-Hao Lee: HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction. ISLPED 2004: 114-119
- [c8]Tse-Tsung Shih, Chia-Lin Yang, Yi-Shin Tung: Workload Characterization of the H.264/AVC Decoder. PCM (2) 2004: 957-966
- [c7]Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang: Profit-driven uniprocessor scheduling with energy and timing constraints. SAC 2004: 834-840
- 2003
- [c6]Yen-Jen Chang, Chia-Lin Yang, Feipei Lai: A power-aware SWDR cell for reducing cache write power. ISLPED 2003: 14-17
- 2002
- [c5]Chia-Lin Yang, Alvin R. Lebeck: A Programmable Memory Hierarchy for Prefetching Linked Data Structures. ISHPC 2002: 160-174
- [c4]Wan-Chun Ma, Chia-Lin Yang: Using Intel Streaming SIMD Extensions for 3D Geometry Processing. IEEE Pacific Rim Conference on Multimedia 2002: 1080-1087
- 2000
- [j1]Chia-Lin Yang, Barton Sano, Alvin R. Lebeck: Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions. IEEE Trans. Computers 49(9): 934-946 (2000)
- [c3]Chia-Lin Yang, Alvin R. Lebeck: Push vs. pull: data movement for linked data structures. ICS 2000: 176-186
1990 – 1999
- 1999
- [c2]Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, Mithuna Thottethodi: Annotated Memory References: A Mechanism for Informed Cache Management. Euro-Par 1999: 1251-1254
- 1998
- [c1]Chia-Lin Yang, Barton Sano, Alvin R. Lebeck: Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. MICRO 1998: 14-24
Coauthor Index
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last updated on 2013-06-11 21:48 CEST by the dblp team