| 2013 | ||
|---|---|---|
| j13 | Tamer A. Ali, Robert J. Drost, Ron Ho, Chih-Kong Ken Yang: A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding. J. Solid-State Circuits 48(4): 1085-1098 (2013) | |
| j12 | Henry Park, Chih-Kong Ken Yang: An INL Yield Model of the Digital-to-Analog Converter. IEEE Trans. on Circuits and Systems 60-I(3): 582-592 (2013) | |
| c10 | Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang: A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS. ISSCC 2013: 38-39 | |
| 2012 | ||
| j11 | E.-Hung Chen, Ramy Yousry, Chih-Kong Ken Yang: Power Optimized ADC-Based Serial Link Receiver. J. Solid-State Circuits 47(4): 938-951 (2012) | |
| j10 | Henry Park, Chih-Kong Ken Yang: Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter. IEEE Trans. on Circuits and Systems 59-II(9): 563-567 (2012) | |
| c9 | Ming-Shuan Chen, Chih-Kong Ken Yang: A low-power highly multiplexed parallel PRBS generator. CICC 2012: 1-4 | |
| c8 | Fengbo Ren, Henry Park, Richard Dorrance, Yuta Toriyama, Chih-Kong Ken Yang, Dejan Markovic: A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs). ISQED 2012: 275-282 | |
| 2011 | ||
| j9 | Jaeha Kim, E.-Hung Chen, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Jared Zerbe, Chih-Kong Ken Yang: Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links. IEEE Trans. on Circuits and Systems 58-I(9): 2096-2107 (2011) | |
| j8 | Amr Amin Hafez, Chih-Kong Ken Yang: Design and Optimization of Multipath Ring Oscillators. IEEE Trans. on Circuits and Systems 58-I(10): 2332-2345 (2011) | |
| j7 | Jintae Kim, S. Limotyrakis, Chih-Kong Ken Yang: Multilevel Power Optimization of Pipelined A/D Converters. IEEE Trans. VLSI Syst. 19(5): 832-845 (2011) | |
| c7 | Tamer A. Ali, Amr Amin Hafez, Robert J. Drost, Ronald Ho, Chih-Kong Ken Yang: A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning. ISSCC 2011: 466-468 | |
| 2010 | ||
| j6 | Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang: A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology. J. Solid-State Circuits 45(4): 781-792 (2010) | |
| j5 | Jintae Kim, Lieven Vandenberghe, Chih-Kong Ken Yang: Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1823-1827 (2010) | |
| j4 | Vladimir Stojanovic, Chih-Kong Ken Yang, Ron Ho: Guest Editorial for Special Issue on High-Performance Multichip Interconnections. IEEE Trans. on Circuits and Systems 57-II(5): 317-318 (2010) | |
| j3 | E.-Hung Chen, Chih-Kong Ken Yang: ADC-Based Serial I/O Receivers. IEEE Trans. on Circuits and Systems 57-I(9): 2248-2258 (2010) | |
| c6 | Tamer A. Ali, Dinesh Patil, Frankie Liu, Elad Alon, Jon K. Lexau, Chih-Kong Ken Yang, Ron Ho: Clocking Links in Multi-chip Packages: A Case Study. Hot Interconnects 2010: 96-103 | |
| 2009 | ||
| c5 | ||
| c4 | Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang: A nonlinear phase detector for digital phase locked loops. CICC 2009: 335-338 | |
| c3 | James R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi: A stochastic jitter model for analyzing digital timing-recovery circuits. DAC 2009: 116-121 | |
| 2008 | ||
| j2 | Utku Seckin, Chih-Kong Ken Yang: A Comprehensive Delay Model for CMOS CML Circuits. IEEE Trans. on Circuits and Systems 55-I(9): 2608-2618 (2008) | |
| 2007 | ||
| j1 | Jaeseo Lee, Geoff Hatcher, Lieven Vandenberghe, Chih-Kong Ken Yang: Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies. IEEE Trans. VLSI Syst. 15(9): 1017-1027 (2007) | |
| c2 | Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang: Device-circuit co-optimization for mixed-mode circuit design via geometric programming. ICCAD 2007: 470-475 | |
| 2006 | ||
| c1 | Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojanovic, Chih-Kong Ken Yang: Power-centric design of high-speed I/Os. DAC 2006: 867-872 | |
Colors in the list of coauthors
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