| 2013 | ||
|---|---|---|
| j3 | Shu-Meng Yang, Meng-Fan Chang, Chi-Chuang Chiang, Ming-Bin Chen, Hiroyuki Yamauchi: Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement. J. Solid-State Circuits 48(2): 611-623 (2013) | |
| 2012 | ||
| c2 | Meng-Fan Chang, Che-Wei Wu, Chia-Chen Kuo, Shin-Jang Shen, Ku-Feng Lin, Shu-Meng Yang, Ya-Chin King, Chorng-Jung Lin, Yu-Der Chih: A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time. ISSCC 2012: 434-436 | |
| 2010 | ||
| j2 | Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin: Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements. J. Solid-State Circuits 45(10): 2142-2155 (2010) | |
| c1 | Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi: A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications. ISSCC 2010: 266-267 | |
| 2009 | ||
| j1 | Meng-Fan Chang, Shu-Meng Yang: Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM. IEEE Trans. VLSI Syst. 17(6): 758-769 (2009) | |
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