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Wei-Bin Yang
2010 – today
- 2011
[j5]Wei-Bin Yang, Chao-Cheng Liao, Yung-Chih Liang: A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process. Microelectronics Journal 42(1): 43-51 (2011)- [j4]Wei-Bin Yang, Chang-Yo Hsieh: A synthesizable pseudo fractional-N clock generator with improved duty cycle output. Microelectronics Journal 42(10): 1099-1106 (2011)
- 2010
- [j3]Wei-Bin Yang, Yu-lung Lo, Ting-Sheng Chao: A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output. IEICE Transactions 93-C(3): 309-316 (2010)
2000 – 2009
- 2009
- [j2]Yu-lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng: High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. IEICE Transactions 92-C(6): 890-893 (2009)
- [j1]Yu-lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng: Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. IEEE Trans. on Circuits and Systems 56-II(5): 339-343 (2009)
- [c8]Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng: 0.5V 160-MHz 260uW all digital phase-locked loop. DDECS 2009: 186-193
- 2008
- [c7]Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-lung Lo, Wei-Bin Yang, Jiunn-Way Miaw: A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS 2008: 64-67
- 2007
- [c6]Chung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien: New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. ISCAS 2007: 3740-3743
- 2006
- [c5]Ting-Sheng Jau, Wei-Bin Yang, Chung-Yu Chang: Analysis and Design of High Performance, Low Power Multiple Ports Register Files. APCCAS 2006: 1453-1456
- [c4]Shu-Chang Kuo, Tzu-Chien Hung, Wei-Bin Yang: The new improved pseudo fractional-N clock generator with 50% duty cycle. ISCAS 2006
- 2005
- [c3]Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang: A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ISCAS (2) 2005: 1174-1177
- 2004
- [c2]Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo: A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. ISCAS (1) 2004: 777-780
- 2001
- [c1]Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung: A low-power high driving ability voltage control oscillator used in PLL. ISCAS (4) 2001: 614-617
Coauthor Index
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last updated on 2012-12-02 20:44 CET by the dblp team