Moritoshi Yasunaga

Masafumi Kuroda, Kunihito Yamamori, Masaharu Munetomo, Moritoshi Yasunaga, Ikuo Yoshihara: A proposal for Zoning Crossover of Hybrid Genetic Algorithms for large-scale traveling salesman problems. IEEE Congress on Evolutionary Computation 2010: 1-6

Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga, Kyrre Glette, Jim Tørresen: An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration. FPT 2008: 169-176

Moritoshi Yasunaga, Yoshiki Yamaguchi, Hiroshi Nakayama, Ikuo Yoshihara, Naoki Koizumi, Jung Hwan Kim: The Segmental-Transmission-Line: Its Design and Prototype Evaluation. ICES 2008: 130-140

Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga: A New Three-Level Tree Data Structure for Representing TSP Tours in the Lin-Kernighan Heuristic. IEICE Transactions 90-A(10): 2187-2193 (2007)

Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga: Implementation of an Effective Hybrid GA for Large-Scale Traveling Salesman Problems. IEEE Transactions on Systems, Man, and Cybernetics, Part B 37(1): 92-99 (2007)

Yoshiki Yamaguchi, Tsutomu Maruyama, Ryuzo Azuma, Moritoshi Yasunaga, Akihiko Konagaya: Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation. VLSI Signal Processing 48(3): 287-299 (2007)

Kyrre Glette, Jim Torresen, Moritoshi Yasunaga: Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA. AHS 2007: 463-470

Kyrre Glette, Jim Torresen, Moritoshi Yasunaga: An Online EHW Pattern Recognition System Applied to Face Image Recognition. EvoWorkshops 2007: 271-280

Kyrre Glette, Jim Torresen, Moritoshi Yasunaga: An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification. ICES 2007: 1-12

Yoshiki Yamaguchi, Noriyuki Aibe, Moritoshi Yasunaga, Yorihisa Yamamoto, Takaaki Awano, Ikuo Yoshihara: Bio-Inspired Functional Asymmetry Camera System. ICONIP (2) 2007: 637-646

Yusuke Arai, Ryo Sawai, Yoshiki Yamaguchi, Tsutomu Maruyama, Moritoshi Yasunaga: A Lattice Gas Cellular Automata Simulator on the Cell Broadband Engine. PARCO 2007: 459-466

Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yoshiki Yamaguchi: On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition. AHS 2006: 373-380

Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga: Realization of the sound space environment for the radiation-tolerant space craft. ReConFig 2006: 198-205

Naoki Koizumi, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga: Variable length segmental-transmission-line and its parameter optimization based on GA. Congress on Evolutionary Computation 2005: 1576-1582

Daekwan Seo, Moritoshi Yasunaga, Insook Kim, Byungwoon Ham, Jung Hwan Kim: Finding transcriptional regulatory elements in Dictyostelium gene expression. Congress on Evolutionary Computation 2005: 1746-1752

Hanxi Zhu, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga: Multi-Modal Neural Networks for Symbolic Sequence Pattern Classification. IEICE Transactions 87-D(7): 1943-1952 (2004)

Noriyuki Aibe, Moritoshi Yasunaga: Reconfigurable I/O interface for mobile equipments. FPT 2004: 359-362

Noriyuki Aibe, Moritoshi Yasunaga: Reconfigurable parallel comparation architecture and its application to IP packet filters. FPT 2003: 363-366

Ryosuke Mizuno, Noriyuki Aibe, Moritoshi Yasunaga, Ikuo Yoshihara: Reconfigurable architecture for probabilistic neural network system. FPT 2003: 367-370

Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim: Gene Finding Using Evolvable Reasoning Hardware. ICES 2003: 198-207

Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara: Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation. Genetic Programming and Evolvable Machines 2(3): 211-230 (2001)

Yong Liu, Kiyoshi Tanaka, Masaya Iwata, Tetsuya Higuchi, Moritoshi Yasunaga (Eds.): Evolvable Systems: From Biology to Hardware, 4th International Conference, ICES 2001 Tokyo, Japan, October 3-5, 2001, Proceedings. Lecture Notes in Computer Science 2210, Springer 2001, isbn 3-540-42671-X

Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim: A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI. DFT 2000: 69-77

Moritoshi Yasunaga, Taro Nakamura, Jung Hwan Kim, Ikuo Yoshihara: Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables. Evolvable Hardware 2000: 253-262

Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara: The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips. FPGA 2000: 116-125

Ikuo Yoshihara, Tomoo Aoyama, Moritoshi Yasunaga: A Fast Model-Building Method for Time Series Using Genetic Programming. GECCO 2000: 537

Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim: Genetic Algorithm-Based Methodology for Pattern Recognition Hardware. ICES 2000: 264-273

Moritoshi Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim: Fault-tolerant self-organizing map implemented by wafer-scale integration. IEEE Trans. VLSI Syst. 6(2): 257-265 (1998)

Hirokazu Koizumi, T. Ochiai, T. Okahashi, Y. Yamashita, A. Maki, T. Yamamoto, Y. Inagami, H. Yoshizawa, M. Iwata, Takashi Omori, Moritoshi Yasunaga: Dynamic Optical Topography and the Real-Time PDP Chip: An Analytical and Synthetical Approach to Higher-Order Brain Functions. ICONIP 1998: 337-340

Moritoshi Yasunaga, Akio Yamada, T. Okahashi: Performance of a bus-based parallel computer with integer-representation processors applied to artificial neural network and parallel AI domains. KES (3) 1998: 519-527

Hiroaki Kitano, Moritoshi Yasunaga: Wafer Scale Integration for Massively Parallel Memory-Based Reasoning. AAAI 1992: 850-856