Hiroto Yasuura

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida: A Selective Replacement Method for Timing-Error-Predicting flip-Flops. Journal of Circuits, Systems, and Computers 21(6) (2012)

Atsushi Shimada, Shigeru Takano, Shigeaki Tagashira, Rin-ichiro Taniguchi, Hiroto Yasuura: WiP Abstract: Estimation of Electric Power Consumption of Individuals by Observing People's Activity. ICCPS 2012: 206

Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS 2012: 138-141

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura: Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI. IEICE Transactions 94-C(4): 520-529 (2011)

Toru Nakamura, Shunsuke Inenaga, Daisuke Ikeda, Kensuke Baba, Hiroto Yasuura: Password Based Anonymous Authentication with Private Information Retrieval. JDIM 9(2): 72-78 (2011)

Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto: Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156

Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura: Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. Signal Processing Systems 60(2): 211-224 (2010)

Ashir Ahmed, Lutfe Kabir, Hiroto Yasuura: An Information Platform for Low-Literate Villagers. AINA 2010: 1271-1277

Toru Nakamura, Shunsuke Inenaga, Daisuke Ikeda, Kensuke Baba, Hiroto Yasuura: An Identifiable Yet Unlinkable Authentication System with Smart Cards for Multiple Services. ICCSA (4) 2010: 236-251

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura: Signal probability control for relieving NBTI in SRAM cells. ISQED 2010: 660-666

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura: A Replacement Strategy for Canary Flip-Flops. PRDC 2010: 227-228

Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura: An RTOS in hardware for energy efficient software-based TCP/IP processing. SASP 2010: 58-63

Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura: Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment. IEICE Transactions 92-C(4): 483-491 (2009)

Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe: Dependable VLSI: device, design and architecture: how should they cooperate? ASP-DAC 2009: 859-860

Noriaki Sakamoto, Mitsuaki Fukase, Tsunenori Mine, Shigeru Kusakabe, Tsuneo Nakanishi, Yoichi Omori, Mohammad Mesbah Uddin, Keijiro Araki, Akira Fukuda, Hiroto Yasuura, Teruaki Kitasuka: Large Scale Business-academia Collaboration in Master Education Course. CSEDU (2) 2009: 159-166

Shunsuke Inenaga, Kenichirou Oyama, Hiroto Yasuura: Towards Modeling Stored-value Electronic Money Systems. NaBIC 2009: 902-907

Tomomi Yamasaki, Shunsuke Inenaga, Daisuke Ikeda, Hiroto Yasuura: Modeling Costs of Access Control with Various Key Management Systems. PDPTA 2009: 676-682

Mohammad Mesbah Uddin, Yasunobu Nohara, Daisuke Ikeda, Hiroto Yasuura: A Multi-Application Smart Card System with Authentic Post-Issuance Program Modification. IEICE Transactions 91-A(1): 229-235 (2008)

Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura: A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V_th variation. Microelectronics Journal 39(12): 1797-1808 (2008)

Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura: A Secure High-Speed Identification Scheme for RFID Using Bloom Filters. ARES 2008: 717-722

Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura: Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI 2008: 403-406

Mohammad Mesbah Uddin, Salahuddin Muhammad Salim Zabir, Yasunobu Nohara, Hiroto Yasuura: A Framework of Authentic Post-Issuance Program Modification for Multi-Application Smart Cards. ICWN 2008: 288-294

Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura: Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS 2008: 62-71

Shinsuke Ohtsuka, Satoshi Kawamoto, Shigeru Takano, Kensuke Baba, Hiroto Yasuura: A Note on Biometrics-based Authentication with Portable Device. SECRYPT 2008: 99-102

Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura: A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ASP-DAC 2007: 878-883

Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura: Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. ESTImedia 2007: 13-18

Tomomi Yamasaki, Toru Nakamura, Kensuke Baba, Hiroto Yasuura: A Door Access Control System with Mobile Phones. PWC 2007: 230-240

Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura: Unlinkability and Real World Constraints in RFID Systems. PerCom Workshops 2007: 371-376

Sozo Inoue, Hiroto Yasuura, Daisuke Hagiwara: Systematic Error Detection for RFID Reliability. ARES 2006: 280-286

Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah: An Energy Characterization Framework for Software-Based Embedded Systems. ESTImedia 2006: 59-64

Takahiro Watanabe, Yasunobu Nohara, Kensuke Baba, Sozo Inoue, Hiroto Yasuura: On Authentication between Human and Computer. PerCom Workshops 2006: 636-639

Kosuke Tarumi, Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura: Bitwidth Optimization for Low Power Digital FIR Filter Design. IEICE Transactions 88-A(4): 869-875 (2005)

Hiroto Yasuura, Shoji Kawahito: Special Section on Papers Selected from AP-ASIC 2004. IEICE Transactions 88-C(8): 1704 (2005)

Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura: A variation-aware low-power coding methodology for tightly coupled buses. ASP-DAC 2005: 557-560

Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura: Toward Unlinkable ID Management for Multi-Service Environments. PerCom Workshops 2005: 115-119

Yasunobu Nohara, Sozo Inoue, Kensuke Baba, Hiroto Yasuura: Quantitative evaluation of unlinkable ID matching schemes. WPES 2005: 55-60

Hiroto Yasuura: Digitally Named World: Challenges for New Social Infrastructures. ISQED 2004: 323

Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura: Reduction of coupling effects by optimizing the 3-D configuration of the routing grid. IEEE Trans. VLSI Syst. 11(5): 951-954 (2003)

Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura: Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid. ASP-DAC 2003: 49-52

Yun Cao, Hiroto Yasuura: Quality-driven design by bitwidth optimization for video applications. ASP-DAC 2003: 532-537

Hiroto Yasuura: Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies. DSD 2003: 17-22

Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura: A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits. DSD 2003: 408-415

Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura: Routing methodology for minimizing 1nterconnect energy dissipation. ACM Great Lakes Symposium on VLSI 2003: 120-123

Hiroto Yasuura (Ed.): Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003. ACM 2003, isbn 0-7803-7660-9

Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura: A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA. DSD 2002: 210-217

Takanori Okuma, Yun Cao, Masanori Muroyama, Hiroto Yasuura: Reducing access energy of on-chip data memory considering active data bitwidth. ISLPED 2002: 88-91

Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura: Power analysis techniques for SoC with improved wiring models. ISLPED 2002: 259-262

Shoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura: A low-power digital matched filter for spread-spectrum systems. ISLPED 2002: 301-306

Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin: An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems. ISSS 2002: 32-37

Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys: Special Session: Security on SoC. ISSS 2002: 192-194

Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao: Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. ISSS 2002: 201-206

Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura: A Power Minimization Technique for Arithmetic Circuits by Cell Selection. VLSI Design 2002: 268-273

Makoto Sugihara, Hiroto Yasuura: Optimization of Test Accesses with a Combined BIST and External Test Scheme. VLSI Design 2002: 683-688

Takanori Okuma, Hiroto Yasuura, Tohru Ishihara: Software Energy Reduction Techniques for Variable-Voltage Processors. IEEE Design & Test of Computers 18(2): 31-41 (2001)

Barry Shackleford, Greg Snider, Richard J. Carter, Etsuko Okushi, Mitsuhiro Yasuda, Katsuhiko Seo, Hiroto Yasuura: A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine. Genetic Programming and Evolvable Machines 2(1): 33-60 (2001)

Yun Cao, Hiroto Yasuura: A system-level energy minimization approach using datapath width optimization. ISLPED 2001: 231-236

Hiroto Yasuura: Editorial. Design Autom. for Emb. Sys. 5(2): 127 (2000)

Akihiko Inoue, Tohru Ishihara, Hiroto Yasuura: Flexible System LSI for Embedded Systems and Its Optimization Techniques. Design Autom. for Emb. Sys. 5(2): 179-205 (2000)

Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura: One language or more?: how can we design an SoC at a system level? ASP-DAC 2000: 653-654

Makoto Sugihara, Hiroto Yasuura, Hiroshi Date: Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. DATE 2000: 134-140

Kei Hirose, Hiroto Yasuura: A Bus Delay Reduction Technique Considering Crosstalk. DATE 2000: 441-445

Tohru Ishihara, Hiroto Yasuura: A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. DATE 2000: 617-623

Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura: An FPGA-based genetic algorithm machine (poster abstract). FPGA 2000: 218

Hajime Yamashita, Hiroto Yasuura, Eko Fajar, Yun Cao: Variable size analysis and validation of computation quality. HLDVT 2000: 95-100

Takanori Okuma, Tohru Ishihara, Hiroto Yasuura: Real-Time Task Scheduling for a Variable Voltage Processor. ISSS 1999: 24-29

Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar: Embedded System Design Using Soft-Core Processor and Valen-C. J. Inf. Sci. Eng. 14(3): 587-603 (1998)

Hiroyuki Tomiyama, Hiroto Yasuura: Module Selection Using Manufacturing Information. ASP-DAC 1998: 275-281

Tohru Ishihara, Hiroto Yasuura: Power-Pro: Programmable Power Management Architecture. ASP-DAC 1998: 321-322

Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura: Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE 1998: 855-860

Tohru Ishihara, Hiroto Yasuura: Voltage scheduling problem for dynamically variable voltage processors. ISLPED 1998: 197-202

Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura: Statistical Performance-Driven Module Binding in High-Level Synthesis. ISSS 1998: 66-71

Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura: Instruction Encoding Techniques for Area Minimization of Instruction ROM. ISSS 1998: 125-130

Makoto Sugihara, Hiroshi Date, Hiroto Yasuura: A novel test methodology for core-based system LSIs and a testing time minimization problem. ITC 1998: 465-472

Hiroyuki Tomiyama, Hiroto Yasuura: Code placement techniques for cache miss rate reduction. ACM Trans. Design Autom. Electr. Syst. 2(4): 410-429 (1997)

Fumio Suzuki, Hisao Koizumi, M. Hiramine, K. Yamamoto, Hiroto Yasuura, K. Okino: A HW/SW co-design environment for multi-media equipments development using inverse problem. CODES 1997: 153-160

Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura: Memory-CPU Size Optimization for Embedded System Designs. DAC 1997: 246-251

Tetsuya Yamada, Hiroto Yasuura: On the Computational Power of Binary Decision Diagram with Redundant Variables. Formal Methods in System Design 8(1): 65-89 (1996)

Tohru Ishihara, Hiroto Yasuura: Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. ISLPED 1996: 117-120

Hiroyuki Tomiyama, Hiroto Yasuura: Size-Constrained Code Placement for Cache Miss Rate Reduction. ISSS 1996: 96-104

Hiroto Yasuura: Foreword. IEICE Transactions 78-D(3): 197-198 (1995)

Hisao Koizumi, Katsuhiko Seo, Fumio Suzuki, Yoshisuke Ohtsuru, Hiroto Yasuura: A Proposal for a Co-design Method in Control Systems Using Combination of Models. IEICE Transactions 78-D(3): 237-247 (1995)

Nikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura: Design Reuse: Fact or Fiction? (Panel). DAC 1994: 562

Takashi Hashimoto, Kazuaki Murakami, Tetsuo Hironaka, Hiroto Yasuura: A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. International Conference on Supercomputing 1993: 308-317

Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura: Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits 1992: 183-192

Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima: NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. DAC 1990: 8-13

M. Ohmura, Hiroto Yasuura, Keikichi Tamaru: Extraction of Functional Information from Combinatorial Circuits. ICCAD 1990: 176-179

Hiroto Yasuura: Locally Computable Coding for Unary Operations. Concurrency: Theory, Language, And Architecture 1989: 312-323

Hiroto Yasuura, Nagisa Ishiura: Semantics of a Hardware Design Language for Japanese Standardization. DAC 1989: 836-839

Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima: High-Speed Logic Simulation on Vector Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 6(3): 305-321 (1987)

Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima: High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. IEEE Trans. Computers 34(9): 789-796 (1985)

Hiroto Yasuura: On Parallel Computational Complexity of Unification. FGCS 1984: 235-243

Hiroto Yasuura, Shuzo Yajima: Hardware Algorithms for VLSI Systems. VLSI Engineering 1984: 105-129

Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima: The Parallel Enumeration Sorting Scheme for VLSI. IEEE Trans. Computers 31(12): 1192-1201 (1982)

Takeshi Sakai, Yoshiyuki Tsuchida, Hiroto Yasuura, Yasushi Ooi, Yoshitsugu Ono, Hiroshi Kano, Shinji Kimura, Shuzo Yajima: An Interactive Simulation System for structured logic design - ISS. DAC 1982: 747-754

Shuzo Yajima, Hiroto Yasuura: Hardware Algorithms and Logic Design Automation. An Overview and Progress Report. RIMS Symposium on Software Science and Engineering 1982: 147-164

Hiroto Yasuura: Width and Depth of Combinational Logic Circuits. Inf. Process. Lett. 13(4/5): 191-194 (1981)