Sungjoo Yoo

Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi: Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches. ASP-DAC 2013: 285-290

Ungjin Jang, Sunggu Lee, Sungjoo Yoo: Optimal wake-up scheduling of data gathering trees for wireless sensor networks. J. Parallel Distrib. Comput. 72(4): 536-546 (2012)

Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi: Active Memory Processor for Network-on-Chip-Based Architecture. IEEE Trans. Computers 61(5): 622-635 (2012)

Hyunsun Park, Sungjoo Yoo, Sunggu Lee: A Multistep Tag Comparison Method for a Low-Power L2 Cache. IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 559-572 (2012)

Suknam Kwon, Sungjoo Yoo, Sunggu Lee, Jinpyo Park: Optimizing Video Application Design for Phase-Change RAM-Based Main Memory. IEEE Trans. VLSI Syst. 20(11): 2011-2019 (2012)

Dongki Kim, Sungkwang Lee, Jaewoong Chung, Daehyun Kim, Dong Hyuk Woo, Sungjoo Yoo, Sunggu Lee: Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU. DAC 2012: 888-896

Youngsik Kim, Sungjoo Yoo, Sunggu Lee: Write performance improvement by hiding R drift latency in phase-change RAM. DAC 2012: 897-906

Suknam Kwon, Dongki Kim, Youngsik Kim, Sungjoo Yoo, Sunggu Lee: A case study on the application of real phase-change RAM to main memory subsystem. DATE 2012: 264-267

Joosung Yun, Sunggu Lee, Sungjoo Yoo: Bloom filter-based dynamic wear leveling for phase-change RAM. DATE 2012: 1513-1518

Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung: Program Phase-Aware Dynamic Voltage Scaling Under Variable Computational Workload and Memory Stall Environment. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 110-123 (2011)

Kyungsu Kang, Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung: Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 30(6): 905-918 (2011)

Hyunsun Park, Sungjoo Yoo, Sunggu Lee: Power management of hybrid DRAM/PRAM-based main memory. DAC 2011: 59-64

Gwangsun Kim, John Kim, Sungjoo Yoo: FlexiBuffer: reducing leakage power in on-chip network routers. DAC 2011: 936-941

Young-Geun Choi, Sungjoo Yoo, Sunggu Lee, Jung Ho Ahn: Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache. DAC 2011: 978-983

Hyunsun Park, Sungjoo Yoo, Sunggu Lee: A novel tag access scheme for low power L2 cache. DATE 2011: 655-660

Dongki Kim, Sungjoo Yoo, Sunggu Lee, Jung Ho Ahn, Hyunuk Jung: A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC. DATE 2011: 1333-1338

Kyungsu Kang, Jongpil Jung, Sungjoo Yoo, Chong-Min Kyung: Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memory. ISQED 2011: 577-582

Kyungsu Kang, Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung: Temperature-Aware Integrated DVFS and Power Gating for Executing Tasks With Runtime Distribution. IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1381-1394 (2010)

Suk-Ju Kang, Sungjoo Yoo, Young Hwan Kim: Dual Motion Estimation for Frame Rate Up-Conversion. IEEE Trans. Circuits Syst. Video Techn. 20(12): 1909-1914 (2010)

Jungsoo Kim, Younghoon Lee, Sungjoo Yoo, Chong-Min Kyung: An analytical dynamic scaling of supply voltage and body bias exploiting memory stall time variation. ASP-DAC 2010: 575-580

Jungsoo Kim, Jaemoon Kim, Giwon Kim, Sangkwon Na, Sungjoo Yoo, Chong-Min Kyung: Event statistics and criticality-aware bitrate allocation to minimize energy consumption of memory-constrained wireless surveillance system. ICME 2010: 7-12

Dongki Kim, Sungjoo Yoo, Sunggu Lee: A Network Congestion-Aware Memory Controller. NOCS 2010: 257-264

Jungsoo Kim, Seungyong Oh, Sungjoo Yoo, Chong-Min Kyung: An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 568-581 (2009)

Minje Jun, Sungjoo Yoo, Eui-Young Chung: Topology Synthesis of Cascaded Crossbar Switches. IEEE Trans. on CAD of Integrated Circuits and Systems 28(6): 926-930 (2009)

Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi: Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus. IEEE Trans. VLSI Syst. 17(8): 1034-1047 (2009)

Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi: Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency. DAC 2009: 806-811

Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung: Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling. DATE 2009: 417-422

Woo-Cheol Kwon, Sungjoo Yoo, Junhyung Um, Seh-Woong Jeong: In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem. DATE 2009: 1058-1063

Jinha Park, Sungjoo Yoo, Sunggu Lee, Chanik Park: Power Modeling of Solid State Disk for Dynamic Power Management Policy Design in Embedded Systems. SEUS 2009: 24-35

Soo-Kwan Eo, Sungjoo Yoo, Kyu-Myung Choi: An industrial perspective of power-aware reliable SoC design. ASP-DAC 2008: 555-557

Minje Jun, Sungjoo Yoo, Eui-Young Chung: Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches. ASP-DAC 2008: 583-588

Woo-Cheol Kwon, Sungjoo Yoo, Sung-Min Hong, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo: A practical approach of memory access parallelization to exploit multiple off-chip DDR memories. DAC 2008: 447-452

Sungpack Hong, Sungjoo Yoo, Byeong Bin, Kyu-Myung Choi, Soo-Kwan Eo, Taehwan Kim: Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution. DATE 2008: 242-247

Woo-Cheol Kwon, Sung-Min Hong, Sungjoo Yoo, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo: An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication. DATE 2008: 1244-1249

Dongwook Lee, Sungjoo Yoo, Kiyoung Choi: Entry control in network-on-chip for memory power reduction. ISLPED 2008: 171-176

Youngchul Cho, Nacer-Eddine Zergainoh, Sungjoo Yoo, Ahmed Amine Jerraya, Kiyoung Choi: Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip. Design Autom. for Emb. Sys. 11(2-3): 167-191 (2007)

Jinyong Jung, Sungjoo Yoo, Kiyoung Choi: Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction. Design Autom. for Emb. Sys. 11(4): 223-247 (2007)

Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi: Communication Architecture Synthesis of Cascaded Bus Matrix. ASP-DAC 2007: 171-177

Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo: PowerViP: Soc power estimation framework at transaction level. ASP-DAC 2006: 551-558

Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo: Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study. CODES+ISSS 2006: 235-240

Sungpack Hong, Sungjoo Yoo, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo: Runtime distribution-aware dynamic voltage scaling. ICCAD 2006: 587-594

Iuliana Bacivarov, Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya: ChronoSym: a new approach for fast and accurate SoC cosimulation. IJES 1(1/2): 103-111 (2005)

Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya: Scheduler implementation in MP SoC design. ASP-DAC 2005: 151-156

Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya: Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model. ASP-DAC 2004: 469-474

Mohamed-Wassim Youssef, Sungjoo Yoo, Arif Sasongko, Yanick Paviot, Ahmed Amine Jerraya: Debugging HW/SW interface for MPSoC: video encoder system design case study. DAC 2004: 908-913

Sungjoo Yoo, Mohamed-Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya, Mario Diaz-Nava: Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software. DATE 2004: 1382-1383

Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, Soo-Ik Chae: An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design. Design Autom. for Emb. Sys. 8(2-3): 119-138 (2003)

Sungjoo Yoo, Ahmed Amine Jerraya: Introduction to Hardware Abstraction Layers for SoC. DATE 2003: 10336-10337

Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya: Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. DATE 2003: 10550-10555

Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh: Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. DATE 2003: 20132-20137

Wander O. Cesário, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Lovic Gauthier, Mario Diaz-Nava: Multiprocessor SoC Platforms: A Component-Based Design Approach. IEEE Design & Test of Computers 19(6): 52-63 (2002)

Gabriela Nicolescu, Kjetil Svarstad, Wander O. Cesário, Lovic Gauthier, Damien Lyonnard, Sungjoo Yoo, Philippe Coste, Ahmed Amine Jerraya: Desiderata pour la spécification et la conception des systèmes électroniques. Technique et Science Informatiques 21(3): 291-314 (2002)

Sunghyun Lee, Sungjoo Yoo, Kiyoung Choi: Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model. CODES 2002: 199-204

Wander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava: Component-based design approach for multicore SoCs. DAC 2002: 789-794

Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya: Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design. DATE 2002: 620-627

Iuliana Bacivarov, Sungjoo Yoo, Ahmed Amine Jerraya: Timed HW-SW cosimulation using native execution of OS and application SW. HLDVT 2002: 51-56

Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo: An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. ISLPED 2002: 84-87

Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu: Validation in a Component-Based Design Flow for Multicore SoCs. ISSS 2002: 162-167

Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya: Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design. VLSI Design 2002: 426-

Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya: Automatic generation and targeting of application-specificoperating systems and embedded systems software. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1293-1301 (2001)

Patrice Gerin, Sungjoo Yoo, Gabriela Nicolescu, Ahmed Amine Jerraya: Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures. ASP-DAC 2001: 63-68

Sungjoo Yoo, Gabriela Nicolescu, Damien Lyonnard, Amer Baghdadi, Ahmed Amine Jerraya: A generic wrapper architecture for multi-processor SoC cosimulation and design. CODES 2001: 195-200

Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed Amine Jerraya: Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. DAC 2001: 518-523

Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya: Automatic generation and targeting of application specific operating systems and embedded systems software. DATE 2001: 679-685

Jinyong Jung, Sungjoo Yoo, Kiyoung Choi: Performance improvement of multi-processor systems cosimulation based on SW analysis. DATE 2001: 749-753

Gabriela Nicolescu, Sungjoo Yoo, Ahmed Amine Jerraya: Mixed-level cosimulation for fine gradual refinement of communication in SoC design. DATE 2001: 754-759

Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya: Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication. HLDVT 2001: 79-82

Sungjoo Yoo, Kiyoung Choi: Optimizing Timed Cosimulation by Hybrid Synchronization. Design Autom. for Emb. Sys. 5(2): 129-152 (2000)

Sungjoo Yoo, Kiyoung Choi, Dong Sam Ha: Performance improvement of geographically distributed cosimulation by hierarchically grouped messages. IEEE Trans. VLSI Syst. 8(5): 492-502 (2000)

Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi: Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. ASP-DAC 2000: 169-174

Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, Kiyoung Choi: Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model. CODES 2000: 77-81

Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi: Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. DATE 2000: 663-668

Sungjoo Yoo, Kiyoung Choi: Optimizing geographically distributed timed cosimulation by hierarchically grouped messages. CODES 1999: 100-104

Byungil Jeong, Sungjoo Yoo, Kiyoung Choi: Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design. FPGA 1999: 247

Sungjoo Yoo, Kiyoung Choi: Optimistic distributed timed cosimulation based on thread simulation model. CODES 1998: 71-75

Sungjoo Yoo, Jinhwan Jeon, Seongsoo Hong, Kiyoung Choi: Hardware-Software Codesign of Resource-Constrained Real-Time Systems. RTCSA 1996: 286-