| 2012 | ||
|---|---|---|
| c10 | Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS 2012: 138-141 | |
| c9 | Krishna Chaitanya Nunna, Farhad Mehdipour, Masayoshi Yoshimura, Kazuaki Murakami: Methodology for early estimation of hierarchical routing resources in 3D FPGAs. VLSI-SoC 2012: 213-218 | |
| 2011 | ||
| c8 | Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga: A Soft Error Tolerance Estimation Method for Sequential Circuits. DFT 2011: 268-276 | |
| c7 | Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto: Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156 | |
| 2010 | ||
| c6 | Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki: Evaluation of transition untestable faults using a multi-cycle capture test generation method. DDECS 2010: 273-276 | |
| 2005 | ||
| c5 | Masayoshi Yoshimura: Implementation of Multiobjective Optimization Procedures at the Product Design Planning Stage. System Modelling and Optimization 2005: 181-191 | |
| 2004 | ||
| c4 | Atsushi Kitazawa, Masayoshi Yoshimura: SemanticObjects and Biomedical Informatics. BIBE 2004: 497-502 | |
| 2002 | ||
| c3 | Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta: A Test Point Insertion Method to Reduce the Number of Test Patterns. Asian Test Symposium 2002: 298-304 | |
| c2 | Masayoshi Yoshimura: Collaborative optimization for product design and manufacturing. CAD 2002: 1-16 | |
| 2001 | ||
| c1 | Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta: Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. ASP-DAC 2001: 485-491 | |
Colors in the list of coauthors
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