Tsutomu Yoshinaga

Hirotaka Kashihara, Hiroki Shimizu, Hiroyoshi Houchi, Masato Yoshimi, Tsutomu Yoshinaga, Hidetsugu Irie: A real-time gait improvement tool using a smartphone. AH 2013: 243

Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga: Design and Implementation of a Handshake Join Architecture on FPGA. IEICE Transactions 95-D(12): 2919-2927 (2012)

Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga: Using Cacheline Reuse Characteristics for Prefetcher Throttling. IEICE Transactions 95-D(12): 2928-2938 (2012)

Akira Egashira, Shunji Satoh, Hidetsugu Irie, Tsutomu Yoshinaga: Parallel Numerical Simulation of Visual Neurons for Analysis of Optical Illusion. ICNC 2012: 130-136

Hidetsugu Irie, Daisuke Fujiwara, Kazuki Majima, Tsutomu Yoshinaga: STRAIGHT: Realizing a Lightweight Large Instruction Window by Using Eventually Consistent Distributed Registers. ICNC 2012: 336-342

Junichi Ohmura, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga: Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster. IEICE Transactions 94-D(12): 2319-2327 (2011)

Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. IJNC 1(2): 244-259 (2011)

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Trans. Computers 60(6): 783-799 (2011)

Takefumi Miyoshi, Hideyuki Kawashima, Yuta Terada, Tsutomu Yoshinaga: A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine. FPL 2011: 490-495

Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga: An Implementation of Handshake Join on FPGA. ICNC 2011: 95-104

Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga: CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection. ICNC 2011: 127-133

Junichi Ohmura, Akira Egashira, Shunji Satoh, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga: Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation. ICNC 2011: 228-234

Takefumi Miyoshi, Kenji Kise, Hidetsugu Irie, Tsutomu Yoshinaga: CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution. ICNC 2010: 71-77

Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Photonic Network-on-Chip. ICNC 2010: 156-161

Qin Wang, Junichi Ohmura, Shan Axida, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga: Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster. ICNC 2010: 243-248

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378

Ben A. Abderazek, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa: The QC-2 parallel Queue processor architecture. J. Parallel Distrib. Comput. 68(2): 235-245 (2008)

Ben A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa: Mathematical Model for Multiobjective Synthesis of NoC Architectures. ICPP Workshops 2007: 36

Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa: High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. The Journal of Supercomputing 38(1): 3-15 (2006)

Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa: Scalable Core-Based Methodology and Synthesizable Core for Systematic Design. ICPP Workshops 2006: 345-352

Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga: Parallel Queue Processor Architecture Based on Produced Order Computation Model. The Journal of Supercomputing 32(3): 217-229 (2005)

Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa: Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. EUC 2005: 340-349

Ta Quoc Viet, Tsutomu Yoshinaga: Asynchronous Parallel Programming Model for SMP Clusters. IASTED PDCS 2005: 355-360

Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa: On the Design of a Register Queue Based Processor Architecture (FaRM-rq). ISPA 2003: 248-262

Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba: A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing. FCCM 2002: 307-308

Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba: Real-Time Medical Diagnosis on a Multiple FPGA-based System. FPL 2002: 1088-1091

Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga: Proposal and Design of a Parallel Queue Processor Architecture (PQP). IASTED PDCS 2002: 549-554

Kanemitsu Ootsu, Tsutomu Yoshinaga, Takanobu Baba: Design and Evaluation of Speculative Multi-threading with Selective Multi-Path Execution. IPDPS 2001: 139

Takanobu Baba, Tsutomu Yoshinaga, Yoshiyuki Iwamoto, Kanemitsu Ootsu: Design, Implementation and Evaluation of a Parallel Object-Oriented Language A-NETL. Scalable Computing: Practice and Experience 3(2) (2000)

Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Sayuri Nakamura, Kanemitsu Ootsu, Takanobu Baba: Recover-X: An Adaptive Router with Limited Escape Channels. ICPADS 2000: 272-279

Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Y. Yamaguchi, Kanemitsu Ootsu, Takanobu Baba: A Cost and Performance Comparison for Wormhole Routers based on HDL Designs. ICPADS 1998: 375-382

Takanobu Baba, Yasushige Furuya, Tsutomu Yoshinaga: Event-based debugging system for a parallel object-oriented language A-NETL. Systems and Computers in Japan 28(11): 53-63 (1997)

Lawrence Mutenda, Manabu Hiyama, Tsutomu Yoshinaga, Takanobu Baba: Parallel Navigation in an A-NETL Based Parallel OODBMS. ISHPC 1997: 305-316

Tsutomu Yoshinaga, Takanobu Baba: Node processor for a parallel object-oriented total architecture A-NET. Systems and Computers in Japan 27(10): 1-13 (1996)

Takanobu Baba, Norihito Saitoh, Takahiro Furuta, Hiroshi Taguchi, Tsutomu Yoshinaga: A Declarative Synchronization Mechanism for Parallel Object-Oriented Computation. IEICE Transactions 78-D(8): 969-981 (1995)

Takanobu Baba, Tsutomu Yoshinaga, Takahiro Furuta: Programming and Debugging for Massively Parallelism: The Case for a Parallel Object-Oriented Language A-NETL. OBPDC 1995: 38-58

Takanobu Baba, Tsutomu Yoshinaga, Tohru Iijima, Yoshifumi Iwamoto, Masahiro Hamada, Mitsuru Suzuki: A parallel object-oriented total architecture: A-NET. SC 1990: 276-285

Takanobu Baba, Yoshifumi Iwamoto, Tsutomu Yoshinaga: A network-topology independent task allocation strategy for parallel computers. SC 1990: 878-887