| 2006 | ||
|---|---|---|
| c14 | Ryosuke Hosaka, Yutaka Sakai, Tohru Ikeguchi, Shuji Yoshizawa: Different Responses of Two Types of Class II Neurons for Fluctuated Inputs. ICCSA (1) 2006: 596-604 | |
| c13 | Ryosuke Hosaka, Tohru Ikeguchi, Yutaka Sakai, Shuji Yoshizawa: A new classification of neuron models for random inputs on bifurcation structures. ISCAS 2006 | |
| 2004 | ||
| j5 | Yutaka Sakai, Kaoru Nakano, Shuji Yoshizawa: Synaptic regulation on various STDP rules. Neurocomputing 58-60: 351-357 (2004) | |
| 2000 | ||
| c12 | Kazuyuki Hiraoka, Ken-ichi Hidai, Masashi Hamahira, Hiroshi Mizoguchi, Tanaka Mishima, Shuji Yoshizawa: Successive Learning of Linear Discriminant Analysis: Sanger-Type Algorithm. ICPR 2000: 2664-2667 | |
| c11 | Kazuyuki Hiraoka, Shuji Yoshizawa, Ken-ichi Hidai, Masashi Hamahira, Hiroshi Mizoguchi, Taketoshi Mishima: Convergence Analysis of Online Linear Discriminant Analysis. IJCNN (3) 2000: 387-391 | |
| 1999 | ||
| j4 | Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi: The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing. IEEE Trans. Computers 48(6): 628-639 (1999) | |
| 1998 | ||
| c10 | Masahiro Murakawa, Shuji Yoshizawa, Toshio Adachi, Shiro Suzuki, Kaoru Takasuka, Masaya Iwata, Tetsuya Higuchi: Analogue EHW Chip for Intermediate Frequency Filters. ICES 1998: 134-143 | |
| c9 | Masahiro Murakawa, Kazuyuki Hiraoka, Tetsuya Higuchi, Tatsumi Furuya, Shuji Yoshizawa: Adaptive Blind Equalization Using Bottleneck Networks Implemented by Evolvable Hardware. ICONIP 1998: 89-92 | |
| c8 | Kazuyuki Hiraoka, Shuji Yoshizawa: Recalling of Many-Valued Functions by Successive Iteration on Bottleneck Networks. ICONIP 1998: 1389-1392 | |
| c7 | Satoshi Morinaga, Shuji Yoshizawa: Control of Spurious Memories by Using Self-Coupling Weights. ICONIP 1998: 1446-1449 | |
| 1997 | ||
| c6 | Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Tetsuya Higuchi: On-line Adaptation of Neural Networks with Evolvable Hardware. ICGA 1997: 792-800 | |
| c5 | Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Tetsuya Higuchi: Evolvable Hardware for Generalized Neural Networks. IJCAI 1997: 1146-1155 | |
| 1996 | ||
| c4 | Masahiro Murakawa, Shuji Yoshizawa, Tetsuya Higuchi: Adaptive Equalization of Digital Communication Channels Using Evolvable Hardware. ICES 1996: 379-389 | |
| c3 | Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Tatsumi Furuya, Masaya Iwata, Tetsuya Higuchi: Hardware Evolution at Function Level. PPSN 1996: 62-71 | |
| 1993 | ||
| j3 | Shuji Yoshizawa, Masahiko Morita, Shun-ichi Amari: Capacity of associative memory using a nonmonotonic neuron model. Neural Networks 6(2): 167-176 (1993) | |
| 1992 | ||
| c2 | Noboru Murata, Shuji Yoshizawa, Shun-ichi Amari: Learning Curves, Model Selection and Complexity of Neural Networks. NIPS 1992: 607-614 | |
| 1991 | ||
| j2 | Kenji Doya, Shuji Yoshizawa: Neural network model of temporal pattern memory. Systems and Computers in Japan 22(9): 61-69 (1991) | |
| c1 | Kenji Doya, Shuji Yoshizawa: Adaptive Synchronization of Neural and Physical Oscillators. NIPS 1991: 109-116 | |
| 1989 | ||
| j1 | Kenji Doya, Shuji Yoshizawa: Adaptive neural oscillator using continuous-time back-propagation learning. Neural Networks 2(5): 375-385 (1989) | |
Colors in the list of coauthors
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