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Mingyan Yu
2010 – today
- 2012
[c18]Pengfei Gou, Bing Yang, Mingyan Yu, Zhigang Mao: Novel O-GEHL Based Hyperblock Predictor for EDGE Architectures. NAS 2012: 172-180- 2011
- [c17]Yongsheng Wang, Yuanhong Li, Mingyan Yu: A 16 bit low voltage low power Delta Sigma modulator. EMEIT 2011: 3178-3181
- [c16]
- 2010
- [c15]Pengfei Gou, Qingbo Li, Yinghan Jin, Qi Zheng, Bing Yang, Mingyan Yu, Jinxiang Wang: M5 based EDGE architecture modeling. ICCD 2010: 289-296
- [c14]Fangfa Fu, Siyue Sun, Xin'an Hu, Junjie Song, Jinxiang Wang, Mingyan Yu: MMPI: A flexible and efficient multiprocessor message passing interface for NoC-based MPSoC. SoCC 2010: 359-362
2000 – 2009
- 2009
- [c13]Zhiqiang Gao, Jinxiang Wang, Fengchang Lai, Mingyan Yu, Zhongzhao Zhang: Wideband reconfigurable CMOS Gm-C filter For wireless applications. ICECS 2009: 179-182
- 2008
- [j1]Zhiqiang Gao, Jianguo Ma, Mingyan Yu, Yizheng Ye: A Fully Integrated CMOS Active Bandpass Filter for Multiband RF Front-Ends. IEEE Trans. on Circuits and Systems 55-II(8): 718-722 (2008)
- 2006
- [c12]Qianneng Zhou, Fengchang Lai, Mingyan Yu: Embedded DC-DC Voltage Down Converter for Low-Power VLSI Chip. APCCAS 2006: 670-673
- [c11]Zhiyuan Li, Mingyan Yu, Jianguo Ma: A Novel Input Stage Based on DTMOS for Low-Voltage Low-Noise Operational Amplifier. APCCAS 2006: 1591-1594
- [c10]Tong Zhou, Zhibo Zhou, Mingyan Yu, Yizheng Ye: Design of A Low Power High Entropy Chaos-Based Truly Random Number Generator. APCCAS 2006: 1955-1958
- [c9]Zhiyuan Li, Fengchang Lai, Mingyan Yu: Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technology. ACM Great Lakes Symposium on VLSI 2006: 123-126
- [c8]Qianneng Zhou, Fengchang Lai, Mingyan Yu: On-chip 3.3V-to-1.8V voltage down converter for low-power VLSI chips. ACM Great Lakes Symposium on VLSI 2006: 140-143
- [c7]Zhiqiang Gao, Mingyan Yu, Yizheng Ye, Jianguo Ma: A CMOS bandpass filter with wide-tuning range for wireless applications. ISCAS 2006
- [c6]Guochi Huang, Tae-Sung Kim, Byung-Sung Kim, Mingyan Yu, Yizheng Ye: Post linearization of CMOS LNA using double cascade FETs. ISCAS 2006
- [c5]Tong Zhou, Mingyan Yu, Yizheng Ye: A Pipelined Switched-Current Chaotic System for the High-Speed Truly Random Number Generation in Crypto Processor. VLSI Design 2006: 216-221
- [c4]Zhiyuan Li, Mingyan Yu, Jianguo Ma: A Rail-to-Rail I/O Operational Amplifier with 0.5% gm Fluctuation Using Double P-channel Differential Input Pairs. VLSI Design 2006: 563-568
- 2005
- [c3]Zhiqiang Gao, Jianguo Ma, Yizheng Ye, Mingyan Yu: Large tuning band range of high frequency filter for wireless applications. ISCAS (1) 2005: 384-387
- [c2]Zhiqiang Gao, Jianguo Ma, Mingyan Yu, Yizheng Ye: A CMOS RF tuning wide-band bandpass filter for wireless applications. SoCC 2005: 79-80
- 2003
- [c1]Yongsheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye: A Test Architecture for System-on-a-Chip. Asian Test Symposium 2003: 506
Coauthor Index
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last updated on 2013-01-09 14:34 CET by the dblp team