Joseph Zambreno

Amit Pande, Joseph Zambreno: Embedded Multimedia Security Systems - Algorithms and Architectures. Springer 2012, isbn 978-1-4471-4458-8, pp. I-XVII, 1-146

Amit Pande, Joseph Zambreno: The secure wavelet transform. J. Real-Time Image Processing 7(2): 131-142 (2012)

Madhu Monga, Manoj Karkee, Song Sun, Lakshmi Kiran Tondehal, Brian L. Steward, Atul G. Kelkar, Joseph Zambreno: Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform. Procedia CS 9: 338-347 (2012)

Chetan Kumar Ng, Sudhanshu Vyas, Jonathan A. Shidal, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones: Improving System Predictability and Performance via Hardware Accelerated Data Structures. Procedia CS 9: 1197-1205 (2012)

Song Sun, Madhu Monga, Phillip H. Jones, Joseph Zambreno: An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs. IEEE Trans. on Circuits and Systems 59-I(1): 113-123 (2012)

Amit Pande, Joseph Zambreno: Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression. ACM Trans. Embedded Comput. Syst. 11(1): 6 (2012)

Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip H. Jones, Joseph Zambreno: Design and evaluation of a delay-based FPGA Physically Unclonable Function. ICCD 2012: 143-146

Chad Nelson, Kevin Townsend, Bhavani Satyanarayana Rao, Phillip H. Jones, Joseph Zambreno: Shepard: A fast exact match short read aligner. MEMOCODE 2012: 91-94

Amit Pande, Joseph Zambreno: Efficient mapping and acceleration of AES on custom multi-core architectures. Concurrency and Computation: Practice and Experience 23(4): 372-389 (2011)

Alex Baumgarten, Michael Steffen, Matthew Clausman, Joseph Zambreno: A case study in hardware Trojan design and implementation. Int. J. Inf. Sec. 10(1): 1-14 (2011)

Song Sun, Joseph Zambreno: Design and Analysis of a Reconfigurable Platform for Frequent Pattern Mining. IEEE Trans. Parallel Distrib. Syst. 22(9): 1497-1505 (2011)

Justin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno: Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection. ICCD 2011: 289-292

Amit Pande, Prasant Mohapatra, Joseph Zambreno: Using Chaotic Maps for Encrypting Image and Video Content. ISM 2011: 171-178

Amit Pande, Joseph Zambreno, Prasant Mohapatra: Architectures for Simultaneous Coding and Encryption Using Chaotic Maps. ISVLSI 2011: 351-352

Alex Baumgarten, Akhilesh Tyagi, Joseph Zambreno: Preventing IC Piracy Using Reconfigurable Logic Barriers. IEEE Design & Test of Computers 27(1): 66-75 (2010)

Amit Pande, Joseph Zambreno: Reconfigurable hardware implementation of a modified chaotic filter bank scheme. IJES 4(3/4): 248-258 (2010)

Abhishek Das, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary: Detecting/preventing information leakage on the memory bus due to malicious hardware. DATE 2010: 861-866

Michael Steffen, Veerendra Allada, Phillip H. Jones, Joseph Zambreno: CANSCID-CUDA. MEMOCODE 2010: 95-98

Michael Steffen, Joseph Zambreno: Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels. MICRO 2010: 237-248

Michael Steffen, Joseph Zambreno: A hardware pipeline for accelerating ray traversal algorithms on streaming processors. SASP 2010: 22-29

Amit Pande, Joseph Zambreno: A Reconfigurable Architecture for Secure Multimedia Delivery. VLSI Design 2010: 258-263

Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno: Providing secure execution environments with a last line of defense against Trojan circuit attacks. Computers & Security 28(7): 660-669 (2009)

Jesse Sathre, Alex Baumgarten, Joseph Zambreno: Architectural Support for Automated Software Attack Detection, Recovery, and Prevention. CSE (2) 2009: 254-261

Eugen Leontie, Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno: Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems. CSE (2) 2009: 830-836

Amit Pande, Joseph Zambreno: Efficient Translation of Algorithmic Kernels on Large-Scale Multi-cores. CSE (2) 2009: 915-920

Amit Pande, Joseph Zambreno: An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform. ISVLSI 2009: 85-90

Michael Steffen, Joseph Zambreno: Design and Evaluation of a Hardware Accelerated Ray Tracing Data Structure. TPCG 2009: 101-108

Jesse Sathre, Joseph Zambreno: Automated software attack recovery using rollback and huddle. Design Autom. for Emb. Sys. 12(3): 243-260 (2008)

Abhishek Das, David Nguyen, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary: An FPGA-Based Network Intrusion Detection Architecture. IEEE Transactions on Information Forensics and Security 3(1): 118-132 (2008)

Abhishek Das, Sanchit Misra, Sumeet Joshi, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary: An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System. DATE 2008: 1160-1165

Song Sun, Zijun Yan, Joseph Zambreno: Experiments in attacking FPGA-based embedded systems using differential power analysis. EIT 2008: 7-12

Amit Pande, Joseph Zambreno: Design and analysis of efficient reconfigurable wavelet filters. EIT 2008: 327-332

Song Sun, Joseph Zambreno: Mining Association Rules with systolic trees. FPL 2008: 143-148

Amit Pande, Joseph Zambreno: Polymorphic wavelet architectures using reconfigurable hardware. FPL 2008: 471-474

Abhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary: Evaluating the effects of cache redundancy on profit. MICRO 2008: 388-398

Song Sun, Michael Steffen, Joseph Zambreno: A Reconfigurable Platform for Frequent Pattern Mining. ReConFig 2008: 55-60

Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary: Microarchitectures for Managing Chip Revenues under Process Variations. Computer Architecture Letters 6(2): 29-32 (2007)

Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary: Microarchitectures for Managing Chip Revenues under Process Variations. Computer Architecture Letters 7(1): 5-8 (2007)

Ramanathan Narayanan, Daniel Honbo, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno: Interactive presentation: An FPGA implementation of decision tree classification. DATE 2007: 189-194

Sailesh Pati, Ramanathan Narayanan, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno: Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction. FPT 2007: 49-56

Ramanathan Narayanan, Berkin Özisikyilmaz, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno: Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads. International Conference on Computational Science (3) 2007: 734-741

Berkin Özisikyilmaz, Ramanathan Narayanan, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary: An Architectural Characterization Study of Data Mining and Bioinformatics Workloads. IISWC 2006: 61-70

Ramanathan Narayanan, Berkin Özisikyilmaz, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary: MineBench: A Benchmark Suite for Data Mining Workloads. IISWC 2006: 182-188

Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari, Nasir D. Memon: SAFE-OPS: An approach to embedded software security. ACM Trans. Embedded Comput. Syst. 4(1): 189-210 (2005)

Joseph Zambreno, Daniel Honbo, Alok N. Choudhary: Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures. FCCM 2005: 333-334

Olga Gelbart, Paul Ott, Bhagirath Narahari, Rahul Simha, Alok N. Choudhary, Joseph Zambreno: CODESSEAL: Compiler/FPGA Approach to Secure Applications. ISI 2005: 530-535

Kripashankar Mohan, Bhagirath Narahari, Rahul Simha, Paul Ott, Alok N. Choudhary, Joseph Zambreno: Performance Study of a Compiler/Hardware Approach to Embedded Systems Security. ISI 2005: 543-548

Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari: Flexible Software Protection Using Hardware/Software Codesign Techniques. DATE 2004: 636-641

Joseph Zambreno, Rahul Simha, Alok N. Choudhary: Addressing application integrity attacks using a reconfigurable architecture. FPGA 2004: 250

Joseph Zambreno, David Nguyen, Alok N. Choudhary: Exploring Area/Delay Tradeoffs in an AES FPGA Implementation. FPL 2004: 575-585

David Nguyen, Joseph Zambreno, Gokhan Memik: Flow Monitoring in High-Speed Networks with 2D Hash Tables. FPL 2004: 1093-1097

Joseph Zambreno: Design and Evaluation of an FPGA Architecture for Software Protection. FPL 2004: 1180

Mahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Joseph Zambreno: Optimizing inter-nest data locality. CASES 2002: 127-135

Joseph Zambreno, Mahmut T. Kandemir, Alok N. Choudhary: Enhancing Compiler Techniques for Memory Energy Optimizations. EMSOFT 2002: 364-381