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 | 2013 | |
|---|---|---|
| j5 |      | Markus Wittmann, Thomas Zeiser, Georg Hager, Gerhard Wellein: Comparison of different propagation steps for lattice Boltzmann methods. Computers & Mathematics with Applications 65(6): 924-935 (2013) |
| i6 | | Markus Wittmann, Georg Hager, Thomas Zeiser, Gerhard Wellein: Asynchronous MPI for the Masses. CoRR abs/1302.4280 (2013) |
| i5 | | Markus Wittmann, Georg Hager, Thomas Zeiser, Gerhard Wellein: An analysis of energy-optimized lattice-Boltzmann CFD simulations from the chip to the highly parallel level. CoRR abs/1304.7664 (2013) |
| 2012 | ||
| c5 | | Faisal Shahzad, Markus Wittmann, Thomas Zeiser, Gerhard Wellein: Asynchronous Checkpointing by Dedicated Checkpoint Threads. EuroMPI 2012: 289-290 |
| 2011 | ||
| j4 | | Johannes Habich, Thomas Zeiser, Georg Hager, Gerhard Wellein: Performance analysis and optimization strategies for a D3Q19 lattice Boltzmann kernel on nVIDIA GPUs using CUDA. Advances in Engineering Software 42(5): 266-272 (2011) |
| i4 | | Markus Wittmann, Thomas Zeiser, Georg Hager, Gerhard Wellein: Comparison of different Propagation Steps for the Lattice Boltzmann Method. CoRR abs/1111.0922 (2011) |
| i3 | | Markus Wittmann, Thomas Zeiser, Georg Hager, Gerhard Wellein: Domain decomposition and locality optimization for large-scale lattice Boltzmann simulations. CoRR abs/1111.1129 (2011) |
| 2009 | ||
| j3 | | Thomas Zeiser, Georg Hager, Gerhard Wellein: Benchmark Analysis and Application Results for Lattice Boltzmann Simulations on NEC SX Vector and Intel Nehalem Systems. Parallel Processing Letters 19(4): 491-511 (2009) |
| c4 | | Gerhard Wellein, Georg Hager, Thomas Zeiser, Markus Wittmann, Holger Fehske: Efficient Temporal Blocking for Stencil Computations by Multicore-Aware Wavefront Parallelization. COMPSAC (1) 2009: 579-586 |
| c3 | | Thomas Zeiser, Georg Hager, Gerhard Wellein: The world's fastest CPU and SMP node: Some performance results from the NEC SX-9. IPDPS 2009: 1-8 |
| 2008 | ||
| j2 | | Stefan Donath, Klaus Iglberger, Gerhard Wellein, Thomas Zeiser, Aditya Nitsure, Ulrich Rüde: Performance comparison of different parallel lattice Boltzmann implementations on multi-core multi-socket systems. IJCSE 4(1): 3-11 (2008) |
| j1 | | Georg Hager, Thomas Zeiser, Gerhard Wellein: Data Access Characteristics and Optimizations for Sun UltraSPARC T2 and T2+ Systems. Parallel Processing Letters 18(4): 471-490 (2008) |
| c2 | | Georg Hager, Thomas Zeiser, Gerhard Wellein: Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers. IPDPS 2008: 1-7 |
| 2007 | ||
| i2 | | Georg Hager, Thomas Zeiser, Gerhard Wellein: Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers. CoRR abs/0712.2302 (2007) |
| i1 | | Georg Hager, Holger Stengel, Thomas Zeiser, Gerhard Wellein: RZBENCH: Performance evaluation of current HPC architectures using low-level and application benchmarks. CoRR abs/0712.3389 (2007) |
| 2004 | ||
| c1 | | Thomas Pohl, Frank Deserno, Nils Thürey, Ulrich Rüde, Peter Lammers, Gerhard Wellein, Thomas Zeiser: Performance Evaluation of Parallel Large-Scale Lattice Boltzmann Applications on Three Supercomputing Architectures. SC 2004: 21 |
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