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 | 2007 | |
|---|---|---|
| c6 |      | Rohit Kapur, Jindrich Zejda, Thomas W. Williams: Fundamentals of timing information for test: How simple can we get? ITC 2007: 1-7 |
| 2006 | ||
| c5 | | Jindrich Zejda, Li Ding: TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks. ISQED 2006: 147-152 |
| 2005 | ||
| c4 | | Alex Gyure, Alireza Kasnavi, Sam C. Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zejda: Noise Library Characterization for Large Capacity Static Noise Analysis Tools. ISQED 2005: 28-34 |
| 2004 | ||
| c3 | | Alireza Kasnavi, Joddy W. Wang, Mahmoud Shahram, Jindrich Zejda: Analytical modeling of crosstalk noise waveforms using Weibull function. ICCAD 2004: 141-146 |
| 2002 | ||
| c2 | | Jindrich Zejda, Paul Frain: General framework for removal of clock network pessimism. ICCAD 2002: 632-639 |
| 1994 | ||
| c1 | | Jindrich Zejda, Eduard Cerny: Gate-level timing verification using waveform narrowing. EURO-DAC 1994: 374-379 |
| 1 | Eduard Cerny | |
| 2 | Li Ding 0002 | |
| 3 | Paul Frain | |
| 4 | Alex Gyure | |
| 5 | Rohit Kapur | |
| 6 | Alireza Kasnavi | |
| 7 | Sam C. Lo | |
| 8 | Mahmoud Shahram | |
| 9 | William Shu | |
| 10 | Peivand F. Tehrani | |
| 11 | Joddy W. Wang | |
| 12 | Thomas W. Williams |
Colors in the list of coauthors
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